PLL Clock Holdover for Noncontact Communication Chips

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Solution Overview

Problem

In noncontact communication systems, the disappearance of a carrier wave leads to the loss of a clock signal, causing communication operations to stop and reducing efficiency, especially when using ASK 100% modulation signals, as existing techniques require serial communication processes and cannot perform SWP communication in parallel with noncontact communication.

Innovation Solution

A semiconductor device with a PLL circuit that maintains an internal clock signal frequency even when the clock signal from the carrier wave is interrupted, using a voltage-controlled oscillation function and phase frequency difference detection circuits to ensure continuous data processing and parallel communication operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If ASK 100% modulation signal is used for noncontact communication, then communication capability is improved, but clock signal extraction becomes unreliable causing internal operations to stop

Engineering Contradiction:
Improvecommunication capabilityVSAvoidclock signal extraction
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The phase frequency difference detection circuit continuously monitors the phase difference between the internal clock signal and the extracted clock signal before the carrier wave disappears. When a disappearance is detected, the circuit has already prepared to switch to using only the internal clock signal, ensuring seamless continuation of internal operations without stopping.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The phase frequency difference detection circuit acts as an intermediary between the extracted clock signal and the internal clock signal. It detects phase differences and controls the switching between these two clock sources, ensuring that internal operations continue reliably even when the extracted clock signal becomes unavailable due to carrier wave disappearance.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Stability of the object's composition

If internal operations are stopped when clock signal is not extracted, then synchronization is maintained, but communication efficiency deteriorates

Engineering Contradiction:
ImprovesynchronizationVSAvoidcommunication efficiency
Core Design Contradiction:
Stability of the object's compositionVSProductivity

Solution Approach 1:

The system dynamically switches between two clock signal sources: the extracted clock signal when the carrier wave is present, and the internal clock signal when the carrier wave disappears. This dynamic adaptation allows the system to maintain synchronization stability while continuing operations without stopping, thereby preserving communication efficiency.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the clock signal parameter by switching from using the extracted clock signal to using the internal clock signal when the carrier wave disappears. This parameter change allows the system to maintain stable synchronization while preventing operational stops, thus improving communication efficiency.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If serial communication process is used for noncontact communication and SWP communication, then communication reliability is improved, but communication efficiency drops conspicuously

Engineering Contradiction:
Improvecommunication reliabilityVSAvoidcommunication efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The internal clock signal continues to operate continuously without stopping, even when the carrier wave disappears and the extracted clock signal becomes unavailable. This continuous operation enables parallel execution of SWP communication and noncontact communication, eliminating the need for serial processing and significantly improving communication efficiency while maintaining reliability.

Inventive Principle:
Principle #20Continuity of useful action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables continuous communication operations and parallel performance of SWP communication even when the clock signal is not extracted from the carrier wave, enhancing communication efficiency by preventing internal operations from stopping and allowing simultaneous data processing.

Implementation Method 1

a noncontact communication semiconductor device (also called NFC chip) uses its communication data and interfaces with another data processing circuit in parallel with noncontact communication by the noncontact communication semiconductor device

Methodology Applied
Scientific EffectElectromagnetic induction: Electromagnetic Induction

Implementation Method 2

a PLL circuit that receives the extracted clock signal and generates the internal clock signal

Methodology Applied
Scientific EffectPhase-locked loop:

Implementation Method 3

the function makes the internal clock signal maintained at a frequency immediately before the interruption

Methodology Applied
Scientific EffectVoltage controlled oscillation:

Data Source

PatentUS8908671B2Semiconductor device, portable communication terminal, IC card, and microcomputer
Publication Date: 2014.12.09 RENESAS ELECTRONICS CORP
  • US8908671B2 patent drawing
  • US8908671B2 patent drawing
  • US8908671B2 patent drawing

AI summary

The present invention provides a noncontact interface technique capable of performing communication operation without stopping an internal operation even when a clock signal cannot be extracted from a carrier wave. In a semiconductor device that receives a modulated carrier wave from an antenna, generates an internal clock signal on the basis of a clock signal extracted from the received carrier wave, and performs operation synchronously with the internal clock signal, a PLL circuit that receives the extracted clock signal and generates the internal clock signal is provided with a voltage control oscillation function. In the case where the clock signal extracted from the carrier wave is discretely interrupted, the function makes the internal clock signal maintained at a frequency immediately before the interruption. With the configuration, even when the clock signal extracted from the carrier wave is interrupted, internal data processes such as decoding and bus interfacing can be continued.