Phase Lock Loop Clock Signal Locking for Motor Startup
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Solution Overview
Problem
Existing motor control systems face challenges in quickly and accurately locking a phase lock loop to the frequency and phase of a motor's back electromotive force (BEMF) signal, which affects the efficiency and vibration minimization in motor operation.
Innovation Solution
A controller system that includes a phase lock loop implemented on a digital signal processor (DSP) IC, utilizing a zero crossing detector, counter, DRC controller, digitally-controlled oscillator, and proportional/integral controller to determine and adjust the clock signal to match the motor's BEMF frequency and phase, thereby minimizing startup time and mechanical vibrations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a phase lock loop is used to generate the clock signal, then the clock can be locked to the motor frequency and phase, but the startup time to achieve locking is prolonged
Solution Approach 1:
The system performs preliminary actions by detecting zero crossings of the BEMF signal during motor startup to pre-determine the initial frequency and phase of the motor. This preliminary information is used to initialize the PLL parameters before formal locking begins, allowing the PLL to start from a near-correct state rather than requiring full acquisition from scratch, thus reducing startup time while maintaining locking accuracy
Solution Approach 2:
A counter measures the number of input clock cycles between zero crossings of the BEMF signal to calculate an initial frequency estimate. This preliminary frequency calculation provides a head start for the PLL, enabling it to converge to the final locked state more quickly without sacrificing precision
2Productivity
If the state machine changes states at a certain rate controlled by a clock, then motor efficiency is improved and mechanical vibration is minimized, but the clock must be accurately locked to the motor BEMF signal which increases system complexity
Solution Approach 1:
The system uses feedback from the BEMF signal's zero crossings to continuously monitor and adjust the clock signal frequency and phase. The PLL compares the input clock with the BEMF-derived reference signal and automatically adjusts parameters to maintain synchronization, ensuring motor efficiency without requiring complex manual tuning or multiple separate control systems
Solution Approach 2:
The phase lock loop serves multiple functions: it generates the clock signal for the state machine, locks to the motor frequency and phase, and provides synchronization reference for the entire motor control system. This multi-functionality reduces the need for separate dedicated circuits while maintaining the required motor efficiency and vibration minimization
Data Source
AI summary
Methods and apparatus to lock a phase lock loop to a spindle motor are disclosed. An example controller comprises a counter to determine a period of an operating signal received from a motor, an oscillator to generate a control signal based on an input signal, and an initializer to generate the input value based on the period, wherein the input value causes the oscillator to generate the control signal having the same phase as the operating signal.