PLL Input Clock Loss Detection Using Delayed Digital Timing
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Solution Overview
Problem
Conventional analog circuits for detecting the loss of an input clock signal in Phase-Locked Loops (PLLs) are influenced by various factors such as resistor values, capacitor effects, and temperature, making them unreliable and in need of a digital solution that is not dependent on voltage references.
Innovation Solution
A digital circuit comprising a time delay circuit, a frequency divider, and digital logic circuits that generate a time-delayed clock signal and indicate the loss of the input clock signal based on the absence of this signal for a specific cycle, ensuring the detection is independent of analog circuit dependencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an analog circuit is used to detect the loss of input clock signal, then the detection function is provided, but the detection reliability deteriorates due to dependence on voltage references influenced by resistor values, capacitor effects, and temperature
Solution Approach 1:
The patent replaces the analog circuit (which uses voltage references, resistors, capacitors, and comparators) with a digital circuit implementation. The digital circuit uses logic gates (NAND gates, inverters) and digital components to detect clock signal loss, eliminating dependence on analog voltage references that are sensitive to temperature and component variations. This substitution of analog for digital resolves the contradiction by improving reliability through digital stability while maintaining acceptable circuit complexity.
2Reliability
If a digital circuit is used to detect the loss of input clock signal, then the detection reliability improves by eliminating voltage reference dependence, but the device complexity increases due to additional digital logic components
Solution Approach 1:
The patent extracts and eliminates the problematic analog components (voltage references, resistors, capacitors, comparators) from the detection circuit, retaining only the essential digital logic functions. By removing the analog voltage reference subsystem and keeping only the digital timing and logic components, the circuit achieves reliable detection without the complexity and sensitivity issues of analog design.
Solution Approach 2:
The patent creates a simplified digital model of the clock signal timing relationship using logic gates that replicate the essential timing function without requiring precise analog voltage comparisons. The digital circuit copies the timing detection function using discrete logic elements that are more stable and predictable than analog voltage references.
Data Source
AI summary
An apparatus is provided for detecting the loss of an input clock signal for a phase-locked loop (PLL). The apparatus includes a time delay circuit, a first frequency divider and a digital logic circuit. The time delay circuit receives the input clock signal and outputs a first time-delayed clock signal. The first frequency divider receives an input signal from an internal clock of the PLL and outputs a clock signal having the same frequency or a lower frequency than that of the time-delayed clock signal. The digital logic circuit that receives the first frequency divider output signal and the first time-delayed clock signal and outputs a signal indicating the loss of the input clock signal if there is no first time-delayed clock signal for a cycle of the first frequency divider output signal.