PLL Clock Distribution Across 3D Chips With Low Jitter Buffering
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In 2.5D or 3D integrated circuit systems, long-distance clock signal propagation faces challenges with high energy consumption and area occupancy due to multiple clocks required for high-performance applications, along with degradation in clock quality due to noise coupling and distribution distance.
Innovation Solution
The system employs a phase lock circuit with integrated LC or ring oscillators and buffering circuits to amplify and maintain the slew rate of clock signals, along with a re-alignment signal path to reduce phase noise and jitter, enabling efficient low-jitter and low-power clock signal distribution across multiple chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple clocks are used to support high-performance applications in 2.5D/3D packaging systems, then the targeted operation frequencies and jitter requirements are met, but area consumption and energy consumption increase significantly
Solution Approach 1:
The patent merges multiple clock sources into a single clock distribution system. A phase lock circuit receives a reference clock signal and generates multiple clock signals with different frequencies through a frequency division mechanism, eliminating the need for multiple separate clock sources while meeting diverse operation frequency requirements across different chips/dies in the 2.5D/3D packaging system
Solution Approach 2:
The phase lock circuit serves multiple functions simultaneously: it acts as a frequency synthesizer to generate different clock frequencies, a phase regulator to maintain signal quality over long distribution distances, and a distribution amplifier to deliver clocks to multiple chips. This multi-functional approach replaces multiple dedicated clock circuits with a single universal clock generation system
2Reliability
If multiple clocks are deployed to meet high-performance requirements, then frequency and jitter specifications are satisfied, but energy consumption increases excessively
Solution Approach 1:
The patent combines multiple clock generation functions into a single phase lock circuit, reducing the total number of active clock sources from multiple to one. This consolidation significantly reduces energy consumption while maintaining the ability to generate multiple frequency outputs for different performance requirements through frequency division and phase regulation
3Adaptability or versatility
If clock signals are distributed over long distances across chips/dies, then comprehensive functions are covered, but clock quality degrades due to noise coupling and distribution distance
Solution Approach 1:
The phase lock circuit acts as an intermediary between the reference clock source and the various chips/dies requiring clock signals. It receives the reference clock, regenerates the signal with proper amplitude and phase characteristics, and distributes it to multiple destinations. This intermediary function compensates for signal degradation over long distribution distances and isolates chips from noise coupling issues
Solution Approach 2:
The phase lock circuit employs feedback mechanisms to continuously monitor and adjust the phase and frequency of distributed clock signals. By comparing the distributed clocks with the reference clock and applying corrective phase adjustments, the system maintains clock quality despite long distribution distances and noise interference across the 2.5D/3D packaging system
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively supports long-distance clock signal distribution with reduced noise and power consumption, maintaining signal quality and accuracy across the integrated circuit system.
Implementation Method 1
The first phase lock circuit comprises an integrated LC or ring oscillator
Implementation Method 2
a first buffering circuit embedded within the first chip for receiving a second periodic signal having the first frequency
Data Source
AI summary
An electrical system is provided. The electrical system comprises a first phase lock circuit embedded within a first chip for receiving a first periodic signal having a first frequency. The electrical system comprises a first buffering circuit embedded within the first chip for receiving a second periodic signal having the first frequency, wherein the first buffering circuit is configured to provide a third periodic signal having the first frequency to an output terminal of the first chip.