PLL Clock Majority Filtering for Radiation-Robust Semiconductors
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Solution Overview
Problem
Semiconductor integrated circuits that generate clock signals face reliability issues, especially in environments with intense radiation, as phase locked loop (PLL) circuits can malfunction, leading to circuit failures.
Innovation Solution
A semiconductor device comprising multiple PLL circuits operating in synchronization, a majority circuit to generate a majority clock signal, and a filter circuit functioning as a low-pass filter to improve clock signal reliability, with variable delay circuits set based on PLL oscillation frequencies to mitigate noise and waveform distortions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple PLL circuits are used to improve reliability in radiation environments, then the reliability of clock signal generation is improved, but the device complexity increases
Solution Approach 1:
The system divides the clock signal generation function into multiple independent PLL circuits (first to N-th PLL circuits) that operate in parallel. Each PLL circuit processes the reference clock signal independently to generate clock signals, allowing the system to tolerate failures in individual segments while maintaining overall functionality through majority voting.
Solution Approach 2:
The patent combines multiple PLL circuits, a majority circuit, and a filter circuit into an integrated clock signal generation system. The majority circuit merges the outputs of multiple PLL circuits by performing majority operations, and the filter circuit further merges and refines these signals to produce a reliable output clock signal.
2Reliability
If a majority circuit and filter circuit are added to process clock signals, then noise is reduced and signal quality is improved, but the device complexity increases
Solution Approach 1:
The majority circuit acts as an intermediary between the multiple PLL circuits and the filter circuit. It performs majority operations on the clock signals to eliminate noise and glitches before passing the cleaned signal to the filter circuit, which further processes the signal to reduce high-frequency noise components.
Solution Approach 2:
The filter circuit changes the frequency characteristics of the clock signal by acting as a low-pass filter, removing high-frequency noise components while preserving the fundamental clock signal. This parameter change in frequency spectrum improves signal quality without fundamentally altering the clock function.
3Reliability
If delay circuits with variable delay time are used to synchronize signals, then the noise filtering effectiveness is improved, but the device complexity increases
Solution Approach 1:
The delay circuit is designed with variable delay time capability, allowing the delay period to be dynamically adjusted based on the oscillation frequency of the PLL circuits. This dynamic adjustment optimizes the synchronization of clock signals and the effectiveness of noise filtering under different operating conditions.
Solution Approach 2:
The system uses feedback mechanisms where the delay time is adjusted based on the oscillation frequency of the PLL circuits. The delay setting circuit monitors the operating frequency and adjusts the delay period accordingly, creating a feedback loop that optimizes noise filtering effectiveness across different frequency ranges.
Data Source
AI summary
A semiconductor device includes first to N-th PLL circuits configured to operate in synchronization with a common reference clock signal to output first to N-th clock signals, respectively; a majority circuit that performs a majority operation on the first to N-th clock signals to generate a majority clock signal; and a filter circuit to which the majority clock signal is provided, the filter circuit operating as a low-pass filter to output an output clock signal. N is an odd number of three or more.