PLL Clock Configuration Using Boot-Time Oscillator Detection
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Solution Overview
Problem
Current processor design is inflexible regarding the choice of reference oscillators, as the division factor in the PLL feedback loop is permanently fixed during manufacturing, limiting the ability to accommodate different frequency reference oscillators without re-tailoring the chip.
Innovation Solution
A circuit that determines the frequency of a first oscillating reference signal using a second reference oscillator, with boot memory storing clock configuration code that operates the processor to adjust the PLL settings dynamically, allowing for flexible selection of reference oscillators and future-proofing the design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If fuse latches are used to fix the division factor during manufacturing, then manufacturing precision is improved, but adaptability deteriorates
Solution Approach 1:
The patent transforms the static, fixed division factor configuration into a dynamic, adjustable parameter. The processor can modify the division factor at runtime based on the detected reference oscillator frequency, allowing the system to adapt to different oscillator choices without requiring physical reconfiguration or re-manufacturing of the chip.
Solution Approach 2:
The invention changes the parameter that is fixed during manufacturing from the division factor itself to the reference oscillator frequency detection capability. By detecting the actual frequency and calculating the appropriate division factor dynamically, the system maintains manufacturing precision while gaining adaptability to different oscillator frequencies.
2Device complexity
If the division factor is permanently fixed during manufacturing, then device complexity is reduced, but ease of operation deteriorates
Solution Approach 1:
The system performs self-configuration by automatically detecting the reference oscillator frequency and calculating the appropriate division factor without requiring external intervention or manual setup. The processor executes code that measures the oscillator frequency and configures the PLL parameters autonomously, simplifying both manufacturing and operation.
Solution Approach 2:
The patent implements preliminary frequency measurement and calculation of the division factor during the boot process, before the system begins normal operation. This preliminary configuration ensures the PLL is properly set up for the specific oscillator being used, eliminating the need for post-manufacturing reconfiguration.
3Reliability
If fuse latches are used to configure the PLL, then reliability is improved, but adaptability deteriorates
Solution Approach 1:
The system implements feedback by measuring the actual reference oscillator frequency and using this information to adjust the division factor. The processor continuously monitors the oscillator characteristics and configures the PLL parameters accordingly, ensuring reliable operation while adapting to different oscillator types and frequencies chosen by the customer.
Data Source
AI summary
A circuit and method for determining the frequency of a first oscillating reference signal generated by a first reference oscillator. The circuit comprises: a second reference oscillator arranged to generate a second oscillating reference signal having a known frequency, a boot memory storing boot code comprising clock configuration code, and a processor coupled to the boot memory and the second reference oscillator. The processor is arranged to execute the boot code from the boot memory upon booting, wherein when executed the clock configuration code operates the processor to determine the frequency of the first reference signal by reference to the second reference signal.