PLL Output Clock Phase Adjustment Without Glitches
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Solution Overview
Problem
Existing digital signal synchronization systems face challenges in making instantaneous, glitchless phase adjustments to output clocks without affecting frequency synchronization, particularly in scenarios requiring flexible phase adjustments at specific points in the clock cycle and across multiple clocks.
Innovation Solution
A clock generator with a phase locked loop (PLL) and a phase adjustment module that breaks down requested phase adjustments into smaller increments and applies them one cycle at a time, allowing precise timing during the low or high portion of the output cycle, independent of the PLL's frequency lock and bandwidth constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a phase offset is summed into the PLL's phase error input to accomplish phase adjustment, then the phase alignment can be adjusted, but the output movement is limited by the PLL's loop bandwidth and cannot be instantaneous
Solution Approach 1:
The patent extracts the phase adjustment function from the PLL's phase error input path and implements it separately in the output clock path. By summing the phase offset after the PLL output (at the output of the output divider or in the output clock path), the phase adjustment is decoupled from the PLL's bandwidth limitations, enabling instantaneous phase changes without affecting the frequency lock.
2Adaptability or versatility
If the frequency is momentarily adjusted to perform phase adjustment in an NCO/DCO/VCO, then phase movement can be achieved, but it cannot instantaneously apply an arbitrarily large phase step and requires time sensitive control
Solution Approach 1:
The patent introduces an intermediary phase adjustment module that sits between the PLL output and the final output clock. This module receives the desired phase offset and applies it by modifying the output divider behavior or adding a phase offset in the output clock path. This intermediary approach allows arbitrary large phase steps to be applied instantly without requiring complex time-sensitive controller logic to manipulate frequency.
3Speed
If a phase offset is summed directly into the synthesizer's phase input in a DPLL system, then fast phase adjustment is achieved, but large uncontrolled instantaneous phase steps are introduced into the output signal
Solution Approach 1:
The patent implements feedback control by monitoring the actual phase of the output clock and using this information to control when and how phase adjustments are applied. The system includes logic that detects the phase state of the output clock and only applies phase offsets at appropriate moments, ensuring that adjustments do not create harmful glitches while still achieving fast phase changes. This feedback mechanism maintains output signal stability while enabling rapid phase adjustment.
Data Source
AI summary
A clock generator with glitchless phase adjustment having a phase locked loop with a controlled oscillator providing an output representing a phase value. One or more output modules generate one or more output clocks from the output. One or more adjustment modules add a requested phase adjustment to an output clock. The phase adjustment modules are configured to break the requested phase adjustment into smaller increments and apply the increments to an output clock generated in said at the output modules one cycle at a time.