Phase Locked Loop Device for Clock Signal Stability
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Solution Overview
Problem
Phase locked loop devices in electronic devices are adversely affected by power fluctuations and transient noise signals, leading to excessive phase error, jitter, and drift, which can cause undesirable behavior in synchronized modules.
Innovation Solution
A phase locked loop device with a phase detector, charge pump, voltage-controlled oscillator, and divider that measures phase differences between a reference clock signal and an output clock signal, adjusts the frequency and phase, and communicates pulses indicative of phase errors, allowing for continuous adjustment and diagnostic analysis to maintain clock signal parameters within defined limits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a phase locked loop is used to generate clock signals, then clock signal generation is achieved, but power fluctuations and transient noise signals cause excessive phase error, jitter, and drift
Solution Approach 1:
The patent implements a feedback mechanism by continuously measuring the phase difference between the reference clock signal and the output clock signal using a phase detector, and using this measurement to adjust the voltage-controlled oscillator to maintain phase lock and reduce phase error, jitter, and drift caused by power fluctuations and noise
Solution Approach 2:
The patent replaces traditional analog phase detection and measurement methods with a digital implementation, where the phase detector outputs a digital signal representing phase difference, which is then processed digitally to control the voltage-controlled oscillator, improving immunity to noise and power fluctuations
2Adaptability or versatility
If phase locked loops are used in multiple processor cores, then each core can have dedicated clock signals, but power fluctuations affect each phase locked loop adversely
Solution Approach 1:
The patent segments the clock generation function by providing separate phase locked loops for different processor cores and device modules, allowing each to operate independently with its own reference clock signal while maintaining similar architectural implementations to ensure consistent performance across all segments
Solution Approach 2:
Each phase locked loop implements continuous feedback measurement of phase difference between reference and output clock signals, allowing independent adjustment and compensation for power fluctuations and noise affecting each specific module or processor core
Data Source
AI summary
A phase locked loop device includes a phase detector that measures a difference in phase between a reference clock signal and an output clock signal of the phase locked loop. The phase detector provides a pulse having a width indicative of the phase difference. A phase measurement module determines a digital value based on the pulse width. Accordingly, the digital value provides an indication of the phase difference between the reference clock signal and the output clock signal. A series of the digital values can be recorded to indicate how the phase difference varies over time, thereby providing a useful characterization of device behavior.