PLL Clock Division Using Time Reference Signal for Phase Offsets
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Solution Overview
Problem
Phase-locked loops (PLLs) face challenges in generating divided signals when the reference clock is unavailable, as existing solutions fail to maintain the required phase offset and synchronization in communication systems, particularly in scenarios like telecom systems where continuous clock generation is essential.
Innovation Solution
A clock generation circuit that uses a time reference signal as a substitute for the reference clock, maintaining relative phase differences between divided signals by synchronizing them with a PLL output and employing a multiplexor to select between the reference clock and the time reference signal, ensuring continuous operation even without the reference clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a PLL is used to generate divided signals, then the output clock is locked in phase with the input reference clock, but the system fails when the reference clock becomes unavailable
Solution Approach 1:
The patent introduces a time reference signal as an intermediary substitute when the reference clock becomes unavailable. This mediator allows the PLL to continue generating divided signals by replacing the missing reference clock, thereby maintaining system operation and improving reliability during reference clock failures.
Solution Approach 2:
The system dynamically switches between using the reference clock and the time reference signal based on availability. The PLL adapts its operation mode - normally locked to the reference clock, but capable of transitioning to use the time reference signal when needed, providing versatility and continuous operation.
2Manufacturing precision
If divided signals are generated from PLL output, then each divided signal has a time period that is an integral multiple of the PLL output, but maintaining specified phase offsets becomes impossible when reference clock is unavailable
Solution Approach 1:
The system pre-establishes the time reference signal in advance, synchronized to the PLL output. When the reference clock becomes unavailable, this pre-prepared time reference signal immediately takes over, allowing the divided signals to maintain their specified phase offsets without interruption or loss of precision.
3Reliability
If the reference clock is continuously monitored, then unavailability can be detected, but system complexity increases to handle the switching logic
Solution Approach 1:
The system implements feedback monitoring of the reference clock signal to detect its availability. This feedback mechanism triggers automatic switching between the reference clock and time reference signal, eliminating the need for complex manual control logic while maintaining reliable operation.
Data Source
AI summary
Clock generation circuit generating multiple divided signals satisfying respective desired offsets. A phase locked loop (PLL) is used to generate a PLL output having a frequency which is a desired multiple of that of a reference clock. The circuit divides the PLL output by a corresponding divisor to generate a corresponding divided signal, wherein each divided signal is offset from a common reference by at least an associated desired time offset. The common reference is timed with respect to the reference clock when the reference clock is available and with respect to a time reference signal otherwise. This arrangement is extended to use the internal time reference signal even for the cases where the reference clock is present by blocking the reference clock while the output systems across PLLs are aligned using the internal time reference signal to ensure desired offsets across different PLLs with a small uncertainty.