Multi-Phase PLL Clock Output Selection Without DLL Drift
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Solution Overview
Problem
Phase locked loop (PLL) circuits face challenges in providing stable and reliable multiple clock signals with different phases and frequencies due to undesirable delays introduced by delay-locked loop (DLL) circuits, which can vary with manufacturing processes, operating voltages, and temperature.
Innovation Solution
A PLL circuit with a voltage-controlled oscillator (VCO) generates multiple periodic signals with distinct phases, which are provided in parallel and independently selected by multiplexers to drive external electronic circuits, eliminating the need for a DLL and ensuring stability across varying conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a DLL circuit is used to generate additional output signals with different phases from the main clock signal, then multiple phased clock signals can be provided, but undesirable delays (drift) are introduced that vary with manufacturing processes, operating voltages, and temperature
Solution Approach 1:
The patent extracts the phase shifting function from the traditional DLL-based approach and implements it directly within the PLL circuit. The PLL generates multiple output signals with different phases (e.g., 0°, 90°, 180°, 270°) simultaneously through its internal architecture, eliminating the need for separate DLL circuits that introduce drift. This extraction of the phase shifting capability to the PLL core resolves the reliability issue while maintaining versatility.
Solution Approach 2:
The PLL circuit is designed to perform multiple functions: it generates the main clock signal, produces multiple phased versions of that signal, and provides frequency synthesis capabilities. By making the PLL multi-functional, the patent eliminates the need for separate DLL circuits, thereby improving reliability while maintaining the ability to provide multiple phased clock signals for different applications.
2Adaptability or versatility
If a DLL circuit is used to temporally shift the output signal to provide delay for additional output signals, then multiple clock signals with different phases can be generated, but the device complexity increases
Solution Approach 1:
The patent merges the phase shifting function traditionally performed by separate DLL circuits into the PLL circuit itself. The PLL's feedback loop and phase detector work together with the voltage-controlled oscillator to generate multiple phased outputs simultaneously. This consolidation reduces device complexity by eliminating redundant DLL components while maintaining the ability to generate multiple clock signals with different phases.
3Reliability
If multiple periodic signals are generated in parallel via the VCO, then the PLL provides a simple and reliable method to generate phased clock signals, but additional multiplexers are needed to independently select and apply signals to external circuits
Solution Approach 1:
The patent implements dynamic phase selection through multiplexers that can independently select from multiple phased clock signals generated by the PLL. The multiplexers respond to selection signals from a controller circuit, allowing flexible and dynamic routing of the appropriate phase to different external circuits. This dynamic selection capability maintains reliability by ensuring each external circuit receives a stable, PLL-generated phased signal while adapting to different operational requirements.
Data Source
AI summary
This application is directed to an electronic device including a phase locked loop (PLL) circuit. The PLL includes a voltage-controlled oscillator (VCO) and the PLL is configured to generate a plurality of periodic signals having a first frequency. Optionally, the periodic signals are equally separated in phase to cover an entire period cycle of the first frequency. The electronic device includes a first multiplexer coupled to the PLL, the first multiplexer being external to the PLL. The first multiplexer configured to receive a first selection signal, select a first periodic signal of the plurality of periodic signals based on the first selection signal, and provide the first selected periodic signal to a first clock-driven circuit that is distinct from the PLL. The electronic device further includes a controller circuit coupled to the first multiplexer, the controller circuit being configured to provide the first selection signal to the first multiplexer.