PLL Clock Calibration for PPM-Compliant Transmitter Timing
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Solution Overview
Problem
Conventional clock generation devices face challenges in generating a clock signal with a frequency within a specified ppm range, especially when using a resonator as a low-cost on-board clock source, as it is difficult to control the frequency to conform to the required specification, leading to non-compliant transmitted data.
Innovation Solution
A clock generation device comprising a clock generator, a calculator, and a phase locked loop (PLL) circuit that calculates and adjusts the frequency difference between an on-board clock signal and an externally provided precise clock signal to ensure the output clock signal conforms to the specified frequency ppm range, using a storage unit to store the frequency difference for calibration before data transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a resonator is used as an on-board clock source to reduce cost, then the device cost is reduced, but the frequency control precision deteriorates making it difficult to conform to the required ppm range
Solution Approach 1:
An frequency calibration circuit is introduced as an intermediary component between the resonator and the PLL circuit. This calibration circuit measures the actual frequency of the resonator and generates a compensation value that is fed back to adjust the resonator's operating frequency, enabling low-cost resonators to achieve specification-compliant frequency precision
Solution Approach 2:
A feedback mechanism is implemented where the frequency calibration circuit continuously monitors the resonator frequency, calculates the deviation from the target frequency, and adjusts the resonator control voltage accordingly. This closed-loop feedback system enables automatic frequency tuning to maintain ppm range compliance
2Manufacturing precision
If a crystal is used as an on-board clock source to achieve precise frequency control, then the frequency precision is improved, but the device cost increases
Solution Approach 1:
The invention replaces expensive crystals with cheaper resonators and compensates for the lower inherent precision through an electronic frequency calibration mechanism. This substitution of a cheap component (resonator) plus a calibration system achieves the same functional result as an expensive crystal alone
Solution Approach 2:
The invention dynamically changes the operating parameters of the resonator by adjusting its control voltage based on measured frequency deviations. This parameter adjustment allows the resonator to be tuned to the precise frequency required, achieving crystal-level precision through electronic control rather than relying on the crystal's inherent stability
3Manufacturing precision
If the reference clock signal frequency does not conform to the defined ppm range, then the clock signal frequency cannot meet the specification, but using calibration circuits increases device complexity
Solution Approach 1:
The frequency calibration circuit is merged with the existing PLL circuit structure, sharing common components such as the voltage-controlled oscillator and control logic. This integration allows frequency calibration functionality to be added without proportionally increasing overall device complexity
Solution Approach 2:
The calibration circuit is designed to automatically measure and correct frequency deviations without requiring external intervention or complex control systems. The system self-calibrates by measuring its own resonator frequency and adjusting accordingly, reducing the need for additional complex control mechanisms
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution ensures that the output clock signal's frequency is accurately adjusted to meet the specified ppm range, ensuring compliant data transmission by predetermining and calibrating the frequency difference, thereby meeting the required specifications.
Implementation Method 1
the first PLL circuit is arranged to generate the output clock signal according to a first reference clock signal related to the first clock signal, and a frequency of the output clock signal is changed according to the frequency difference
Data Source
AI summary
A clock generation device provided for a transmitter is provided and comprises a clock generator, a calculator and a first phase locked loop (PLL) circuit. The clock generator generates a first clock signal. The calculator calculates a frequency difference between the first and second clock signals. The first PLL circuit generates an output clock signal according to a first reference clock signal related to the first clock signal, and a frequency of the output clock signal is changed according to the frequency difference. The transmitter transmits data according to the output clock signal.