PLL Clock Frequency Switching Without Lock Time or Phase Drift
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Solution Overview
Problem
Existing PLL-type clock generation circuits require a lock time for frequency changes, making instantaneous frequency switching impossible due to the delay introduced by this lock time, which is a limitation in communications systems that need to support different data rates without data loss.
Innovation Solution
A PLL-type clock generation circuit design that includes a phase and frequency detector, a filter, a voltage-controlled oscillator, and frequency dividers with sampling and selection circuits to enable on-the-fly frequency switching without lock time, maintaining frequency and phase lock, and ensuring glitch-free transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional PLL-type clock generation circuits are used for frequency switching, then frequency stability is maintained through lock time, but instantaneous frequency switching becomes impossible due to the delay introduced by lock time
Solution Approach 1:
The frequency division function is segmented into multiple parallel divider circuits (first frequency divider, second frequency divider, third frequency divider) operating simultaneously at different division ratios. This allows the system to switch between frequencies by selecting which divider output to use, rather than reconfiguring a single divider, thereby eliminating lock time while maintaining phase and frequency lock through the PLL structure.
Solution Approach 2:
Multiple frequency divider circuits are prepared in advance, each configured with a different division ratio. The sampling circuit captures the frequency selection signal at the appropriate moment, and the selection circuit is ready to immediately switch to the pre-configured divider output corresponding to the desired frequency. This preliminary configuration of multiple dividers enables instantaneous frequency switching without requiring lock time for reconfiguration.
2Adaptability or versatility
If frequency switching is performed in conventional PLL circuits, then different data rates can be supported, but data loss occurs during the lock time delay
Solution Approach 1:
The PLL circuit maintains continuous phase and frequency lock throughout the frequency switching process. The phase and frequency detector continuously compares the reference clock with the feedback clock, and the voltage-controlled oscillator continuously adjusts its output frequency based on the error signal. This continuous action ensures that data communication remains uninterrupted and no data is lost during frequency transitions, while still enabling switching between different data rates through the frequency selection circuit.
3Device complexity
If a single frequency divider is used in PLL circuits, then circuit complexity is reduced, but frequency switching requires lock time for reconfiguration
Solution Approach 1:
The frequency division function is segmented into multiple parallel divider circuits (first frequency divider, second frequency divider, third frequency divider) operating simultaneously at different division ratios. This allows the system to switch between frequencies by selecting which divider output to use, rather than reconfiguring a single divider, thereby eliminating lock time while maintaining phase and frequency lock through the PLL structure.
Solution Approach 2:
The system dynamically selects among multiple pre-configured frequency divider outputs based on the frequency selection signal. The selection circuit responds to changes in the frequency selection signal by switching between the outputs of different divider circuits. This dynamic selection mechanism enables instantaneous frequency switching without requiring the divider circuit to be reconfigured, thus eliminating lock time while maintaining relatively simple individual divider circuit designs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables instantaneous frequency switching of clock signals between multiple frequencies without lock time, ensuring continuous data communication and maintaining phase and frequency lock, thus addressing the limitations of existing PLL-type clock generation circuits.
Implementation Method 1
a voltage controlled oscillator responsive to the voltage control signal and adapted to generate an oscillation signal
Implementation Method 2
a phase and frequency detector adapted to detect a difference between a reference clock and a feedback clock
Data Source
AI summary
A difference between a reference clock and feedback clock is detected to generate a difference signal that is filtered to generate a voltage controlled oscillator control signal and produce an oscillation signal having an oscillation frequency. A first frequency dividing circuit divides the oscillation signal by a selected one of a number of first frequency divisors to generate an output signal at a selected frequency. A second frequency dividing circuit divides the output signal by a selected one of a number of second frequency divisors to generate the feedback clock. The frequency divisors are selected by a frequency selection signal. The first frequency dividing circuit samples the frequency selection signal at the rate of the oscillation signal divided by a least common multiple of the plurality of first frequency divisors. The second frequency dividing circuit samples the sampled frequency selection signal at the rate of the feedback clock.