PLL Clock Recovery Switching for High-Speed Data Lock
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Solution Overview
Problem
Conventional PLL circuits face challenges in high-frequency data baud operations, such as difficulty in switching the input differential pair of the charge pump and large static phase offsets due to high VCO frequencies and limited open loop gain during frequency/phase detection operations.
Innovation Solution
A system and method that includes a phase-frequency detector, charge pump, phase detector, and active filter with switches to manage frequency acquisition and phase locking modes, using a frequency divider to adjust the oscillator signal and bypassing passive filters in the charge pump and active filters to enhance open loop gain and reduce static phase offsets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a charge pump is used as a loop filter in a conventional PLL circuit, then the circuit can perform frequency acquisition, but the high frequency output signal of the phase detector cannot effectively switch the input differential pair of the charge pump while maintaining reasonable power consumption
Solution Approach 1:
The system dynamically switches between two operational modes: frequency acquisition mode where the charge pump is active for low-frequency operation, and phase lock mode where a bypass path handles high-frequency signals. This dynamic reconfiguration allows the circuit to optimize performance for different frequency ranges without excessive power consumption at any given mode.
Solution Approach 2:
A bypass path with a bypass capacitor is introduced as an intermediary element that provides an alternative signal path for high-frequency components. This bypass path allows the high-frequency output signal to pass through without requiring the charge pump to switch at those frequencies, thereby avoiding the power consumption and switching difficulties associated with high-frequency charge pump operation.
2Measurement precision
If an active filter with input resistors is used in a conventional PLL circuit, then the circuit can perform phase locking, but the open loop gain is significantly reduced when the VCO frequency is much higher than the reference clock frequency, resulting in large static phase offset
Solution Approach 1:
The system dynamically adjusts the operational mode based on frequency conditions. During frequency acquisition when VCO frequency differs significantly from reference clock frequency, the bypass path is activated to maintain high open loop gain. During phase locking when frequencies are closely matched, the system transitions to using the active filter for precise phase detection. This dynamic adaptation ensures both high gain and accurate phase detection under different operating conditions.
Solution Approach 2:
The system changes the effective configuration of the loop filter by switching between the charge pump path and the bypass path based on operating frequency parameters. When the VCO frequency is much higher than the reference clock frequency, the bypass path with capacitor is activated to maintain high open loop gain. When frequencies are closely matched during phase locking, the active filter path is used for accurate phase detection, thus adapting the system parameters to match the operating conditions.
3Adaptability or versatility
If a conventional PLL circuit uses a reference clock with small frequency deviation for frequency acquisition, then the pull-in range is limited, but using the incoming data signal directly as reference after switching causes difficulty in handling high frequency signals
Solution Approach 1:
The system dynamically transitions between two reference sources: initially using a reference clock with small frequency deviation for reliable frequency acquisition within a limited pull-in range, then switching to using the incoming data signal as reference after frequency lock is achieved. The bypass path ensures that high-frequency signals from the phase detector are properly handled during this transition and in the final phase lock mode, maintaining signal processing reliability across the full frequency range.
Data Source
AI summary
In one example, a system includes an oscillator adapted to provide an oscillator signal, a frequency divider adapted to divide the oscillator signal to provide a divided oscillator signal, and a phase-frequency detector adapted to provide phase-frequency detection signals in response to a reference clock signal and the divided oscillator signal. The system also includes a charge pump adapted to provide first output signals in response to the phase-frequency detection signals, a phase detector adapted provide second output signals in response to an incoming data signal and the oscillator signal, and one or more switches adapted to pass the first output signals during a frequency acquisition mode and pass the second output signals during a phase lock mode. The system also includes an active filter adapted to filter the passed first or second output signals. The oscillator is adapted to adjust a frequency of the oscillator signal in response to the filtered first or second output signals.