PLL Clock Scaling in Packet Processing Modules Using FIFO Fill Levels
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Solution Overview
Problem
Conventional packet processing modules operate at fixed clock rates, leading to inefficient power usage and increased cooling requirements due to excessive power consumption, as they do not adapt to varying workload demands.
Innovation Solution
Implement a feedback loop that adjusts the system clock rate based on the fill level of First-In, First-Out (FIFO) buffers, using a Phase-Lock Loop (PLL) to optimize the clock speed according to processing demands, ensuring the module operates at the minimum necessary rate to avoid overflow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If fixed clock rates are used in packet processing modules, then the module can process packets at maximum speed, but power consumption increases and cooling requirements increase
Solution Approach 1:
The patent applies dynamics by transitioning from fixed clock rates to dynamically adjustable clock rates. The system continuously monitors FIFO fill levels and adjusts the clock rate in real-time to match actual processing demands, allowing the module to operate at maximum speed when needed and at lower speeds when workload is light, thereby resolving the contradiction between productivity and power consumption
Solution Approach 2:
The patent changes the clock rate parameter based on system load conditions. By monitoring FIFO fill levels and adjusting the clock rate parameter accordingly, the system optimizes the balance between processing speed and power consumption, implementing variable clock rates rather than fixed rates to adapt to varying workload demands
2Productivity
If fixed clock rates are used in packet processing modules, then the module can process packets at maximum speed, but cooling requirements and heat dissipation increase
Solution Approach 1:
The system dynamically adjusts clock rates based on actual processing needs, reducing operational speed and consequently heat generation during low-demand periods while maintaining maximum speed capability during high-demand periods, thus resolving the contradiction between productivity and temperature management
3Use of energy by moving object
If the clock rate is continuously adjusted based on FIFO fill level, then power consumption is minimized, but system complexity increases due to feedback loop requirements
Solution Approach 1:
The patent implements a feedback mechanism that monitors FIFO fill levels and uses this information to adjust clock rates. This feedback loop enables the system to optimize power consumption by matching clock speed to actual workload, accepting increased complexity as a trade-off for significant power savings
Solution Approach 2:
The system performs self-adjustment by automatically monitoring its own FIFO fill levels and adjusting its clock rate without external intervention. This self-service capability allows the system to optimize its own power consumption while managing the complexity internally
Data Source
AI summary
An apparatus includes circuitry configured to receive a fill level from N first-in, first-out (FIFOs), N is an integer that is greater than or equal to 1, determine a module clock speed based on the fill level, and program a phase lock loop (PLL) based on the determined module clock speed where the PLL provides a module clock at the module clock speed to a packet processing circuit configured to receive packets from the N FIFOs. A packet processing module includes N FIFOs. N is an integer that is greater than or equal to 1; a programming state machine configured to receive a fill level from the N FIFOs and to program a PLL based thereon; and a packet processing circuit configured to receive packets from the N FIFOs, wherein the packet processing circuit receives a module clock from the PLL with a speed determined by the programming state machine.