Reception Circuit PLL Clock Switching for High-Speed Self-Test
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Solution Overview
Problem
High-frequency compatible LSI testers are expensive, leading to increased manufacturing costs and circuit size due to the requirement of a PLL circuit for test purposes in semiconductor integrated circuits.
Innovation Solution
A semiconductor device with multiple reception circuit blocks, each equipped with a phase-locked loop (PLL) circuit generating a clock signal, a selector for switching between internal and external clock signals based on a test mode signal, and a signal processing circuit performing operations in synchronization with the selected clock signal, allowing for high-speed testing without relying on external LSI tester frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a PLL circuit is added for test purposes to enable high-frequency testing, then testing capability is improved, but circuit size increases
Solution Approach 1:
The patent makes the existing PLL circuit, originally designed only for normal operation, serve dual purposes by enabling it to generate test clock signals at high frequencies. The test control circuit activates the PLL circuit to operate at a frequency higher than the rated frequency to generate a test clock signal, allowing the same circuit to fulfill both normal operation and testing functions without adding dedicated test-only PLL circuits.
Solution Approach 2:
The semiconductor integrated circuit performs self-testing by using its own internally generated test clock signal from the PLL circuit, eliminating the need for external high-frequency clock sources or additional test-specific oscillation circuits. The device tests itself by supplying the generated test clock signal to the switching circuit and signal processing circuit under test control.
2Productivity
If a PLL circuit is added for test purposes to enable high-frequency testing, then testing capability is improved, but manufacturing cost increases
Solution Approach 1:
The patent makes the existing PLL circuit, originally designed only for normal operation, serve dual purposes by enabling it to generate test clock signals at high frequencies. The test control circuit activates the PLL circuit to operate at a frequency higher than the rated frequency to generate a test clock signal, allowing the same circuit to fulfill both normal operation and testing functions without adding dedicated test-only PLL circuits.
Solution Approach 2:
The semiconductor integrated circuit performs self-testing by using its own internally generated test clock signal from the PLL circuit, eliminating the need for external high-frequency clock sources or additional test-specific oscillation circuits. The device tests itself by supplying the generated test clock signal to the switching circuit and signal processing circuit under test control.
3Measurement precision
If the LSI tester supplies external clock signal at rated frequency, then testing accuracy is improved, but the tester becomes expensive
Solution Approach 1:
The semiconductor integrated circuit performs self-testing by using its own internally generated test clock signal from the PLL circuit, eliminating the need for external high-frequency clock sources or additional test-specific oscillation circuits. The device tests itself by supplying the generated test clock signal to the switching circuit and signal processing circuit under test control.
Solution Approach 2:
The patent changes the operating frequency parameter of the existing PLL circuit beyond its rated frequency to generate high-frequency test clock signals. The test control circuit enables the PLL circuit to operate at frequencies higher than the rated frequency, transforming the circuit's operational parameters to achieve testing capability without requiring specialized expensive equipment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables high-speed operation testing with reduced circuit size and cost by using internally generated high-frequency clock signals, eliminating the need for additional oscillation circuits and expensive LSI testers.
Implementation Method 1
Each of the plurality of reception circuit blocks includes a phase-locked loop (PLL) circuit generating a clock signal phase-synchronized with a data signal received by itself
Data Source
AI summary
The disclosure provides a semiconductor device including a plurality of reception circuit blocks each individually receiving a data signal, performing predetermined signal processing for the received data signal, and receiving a test mode signal for instructing a normal operation or a test operation. Each of the plurality of reception circuit blocks includes a PLL circuit generating a clock signal phase-synchronized with a data signal received by itself; a first selector selecting, based on the test mode signal, one of the clock signal generated by the PLL circuit of a different reception circuit block other than a reception circuit block of itself of the plurality of reception circuit blocks and the clock signal generated by the PLL circuit of the reception circuit block of itself, and a signal processing circuit performing the predetermined signal processing in synchronization with the clock signal selected by the first selector.