PLL Clock Synthesizer With Single-Loop Duty Cycle Phase Control
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Solution Overview
Problem
Existing methods for correcting duty cycle errors in clock signals are inefficient, requiring lengthy iterative adjustments and consuming high power, and are unable to correct errors quickly enough for rapidly rising system clock speeds.
Innovation Solution
A Duty Cycle Corrected Phase Interpolator (DCCPI) circuit that adjusts both phase and duty cycle of a clock signal in a single loop using a Phase Locked Loop (PLL), buffer, and clock tree, with digital and analog control, to achieve a nearly 50% duty cycle by processing feedback loops and weighted sums of multi-phases clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If iterative adjustment of delays is used to correct duty cycle error, then duty cycle accuracy is improved, but correction time increases significantly
Solution Approach 1:
The patent pre-calculates and stores optimal delay values in a lookup table before operation. When duty cycle correction is needed, the system directly retrieves the pre-computed delay value instead of performing iterative adjustments, thereby achieving accurate correction without time-consuming iteration.
Solution Approach 2:
The patent replaces the mechanical iterative adjustment process with a digital lookup table system. Instead of physically or electronically tuning delay parameters through multiple cycles, the system uses memory storage and direct retrieval to achieve the same correction goal instantaneously.
2Manufacturing precision
If iterative delay adjustment is used for duty cycle correction, then duty cycle precision is improved, but power consumption increases
Solution Approach 1:
The optimal delay values are pre-calculated and stored in a lookup table during system initialization or manufacturing. During operation, the system only needs to retrieve the stored value, avoiding the continuous power-consuming iterative adjustment process while maintaining high precision.
Solution Approach 2:
The patent substitutes the power-intensive iterative adjustment mechanism with a low-power memory retrieval operation. The lookup table stores pre-optimized delay values that can be accessed with minimal energy expenditure, eliminating the need for continuous active tuning.
3Manufacturing precision
If known duty cycle correction methods are used, then duty cycle control is achieved, but circuit complexity increases
Solution Approach 1:
The lookup table serves multiple functions: it stores delay values for duty cycle correction, provides phase adjustment parameters, and can be programmed to adapt to different operating conditions. This multi-functionality reduces the need for separate correction circuits, thereby simplifying the overall system.
Solution Approach 2:
The patent replaces complex analog delay adjustment circuits with a digital lookup table implementation. This substitution uses simple memory cells and decoders instead of intricate analog components, reducing circuit complexity while maintaining or improving control precision.
Data Source
AI summary
A clock synthesizer is provided. The Clock synthesizer includes a Phase Locked Loop (PLL) configured to generate a clock signal based on a reference signal. A clock buffer is connected to the PLL. The clock buffer stores the clock signal. A Duty Cycle Controller and Phase Interpolator (DCCPI) circuit is connected to the clock buffer. The DCCPI circuit receives the clock signal from the clock buffer, adjusts a duty cycle of the clock signal to substantially equal to 50%, performs phase interpolation on the clock signal, and provides the clock signal as an output after adjusting the duty cycle substantially equal to 50% and performing the phase interpolation.