PLL Reference Clock Detection Using a Sleep Clock
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Solution Overview
Problem
Phase-locked loop (PLL) circuitry in integrated circuits has limited lockable frequency ranges, requiring additional components and increased costs to accommodate multiple reference clock frequencies, which complicates the initialization and locking process.
Innovation Solution
A circuit and method that utilize a clock counter and frequency estimator to determine the reference clock frequency using a sleep clock, allowing selection of the closest frequency from a plurality of allowed frequencies, thereby reducing the need for external pins and associated circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If strap pins are used to encode different reference clock frequencies, then multiple frequencies can be accommodated, but PCB space increases due to additional external resistors
Solution Approach 1:
The patent extracts the frequency encoding function from external strap pins and resistors, moving it entirely into the IC. The frequency detection circuitry internally determines the reference clock frequency without requiring external encoding components, thereby eliminating the need for additional external resistors and reducing PCB space.
Solution Approach 2:
The patent implements a universal frequency detection circuit that can automatically identify and adapt to multiple reference clock frequencies (e.g., 12MHz, 19.2MHz, 24MHz, 38.4MHz, 52MHz) without requiring different external components for each frequency. This multi-functional circuit replaces the frequency-specific strap pin configurations.
2Adaptability or versatility
If strap pins with external resistors are used to encode frequencies, then frequency selection is possible, but on-chip real estate increases for input buffer, ESD, decoder, and associated circuitry
Solution Approach 1:
The patent merges the frequency detection, decoding, and selection functions into a single integrated circuit block. The frequency detection circuit directly interfaces with the PLL without requiring separate input buffers, ESD protection circuits, and decoders that would be needed for strap pin implementations. This consolidation reduces the total on-chip real estate required.
Solution Approach 2:
The frequency detection circuit automatically detects the reference clock frequency and configures the PLL accordingly without requiring external decoding logic or additional control circuitry. The circuit self-configures based on the detected frequency, eliminating the need for external decoders and associated support circuitry.
3Adaptability or versatility
If multiple strap pins and external resistors are used for frequency encoding, then different frequencies can be supported, but manufacturing costs increase
Solution Approach 1:
The patent removes the external frequency encoding components (strap pins and resistors) from the system, consolidating all frequency detection and selection functionality within the IC. This eliminates the need for additional external components that会增加 manufacturing complexity and cost.
Solution Approach 2:
The patent uses an internal sleep clock as a reference for frequency detection, creating a self-contained frequency measurement system that does not require external frequency reference components. This internal reference approach simplifies the bill of materials and reduces manufacturing costs.
4Reliability
If PLL is used with limited lockable frequency ranges, then frequency control is achieved, but additional components are required to accommodate multiple reference clock frequencies
Solution Approach 1:
The patent implements a frequency detection circuit that determines the reference clock frequency before the PLL locking process begins. This preliminary frequency identification allows the system to pre-configure the PLL with the appropriate frequency parameters, ensuring reliable locking without requiring multiple PLL circuits or complex switching mechanisms for different frequencies.
Solution Approach 2:
The frequency detection circuit uses feedback from the sleep clock and reference clock comparison to automatically determine the operating frequency. This feedback mechanism allows the system to self-adjust and configure the PLL for the correct frequency range, maintaining reliable locking across multiple reference frequencies without additional external components.
Data Source
AI summary
Apparatuses, methods, systems, algorithms, and circuits for reference clock frequency determination are disclosed. In one embodiment, a circuit for detecting a reference clock frequency can include a clock counter configured to count a number of cycles of the reference clock over a predetermined portion of a sleep clock to provide a reference clock cycle count, where the sleep clock has a known frequency and a predetermined accuracy; a frequency estimator configured to estimate the reference clock frequency from the reference clock cycle count and the known frequency of the sleep clock; and a frequency selector configured to select a closest frequency to the estimated reference clock frequency from a plurality of allowed frequencies.