PLL Clock Source Switching for Frequency PPM Compliance
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Solution Overview
Problem
Conventional clock generation circuits face challenges in generating an output clock signal within the specified frequency ppm range, particularly when using low-cost resonators, which often fail to conform to the required frequency specifications, leading to non-compliant data transmission.
Innovation Solution
A clock generation circuit that incorporates a multiplexer and phase locked loop (PLL) to selectively switch between a local clock signal generated by a low-cost on-board clock source and a precise external clock signal, ensuring the output clock signal conforms to the defined frequency ppm range by using the precise clock signal when the local clock signal does not meet the specifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a low-cost resonator is used as the clock generator, then the cost is reduced, but the frequency of the reference clock signal cannot conform to the defined ppm range
Solution Approach 1:
The patent employs a low-cost resonator instead of an expensive crystal as the clock generator. While the resonator has lower frequency precision, the system compensates through automatic frequency adjustment mechanisms and spread spectrum clocking to achieve compliance with specifications at reduced cost
Solution Approach 2:
The patent dynamically adjusts the frequency of the reference clock signal by changing operating parameters of the resonator-driven clock generator. This includes voltage-controlled frequency adjustment and temperature compensation to bring the frequency within the required ppm range defined by specifications
2Manufacturing precision
If a crystal is used as the clock generator, then the frequency ppm range is controlled, but the cost increases
Solution Approach 1:
The patent replaces expensive crystals with cheaper resonators as the clock generator. Although resonators have broader frequency tolerance, the system uses frequency adjustment circuits and spread spectrum techniques to achieve the required precision at lower cost
3Ease of manufacture
If the reference clock signal frequency does not conform to the defined ppm range, then the cost is reduced, but the transmitted data does not meet the specification
Solution Approach 1:
The patent incorporates frequency measurement and feedback control mechanisms that continuously monitor the reference clock signal frequency and automatically adjust it to maintain compliance with the defined ppm range, ensuring specification compliance while using cost-effective resonators
Solution Approach 2:
The system dynamically changes operating parameters of the clock generator to adjust the reference clock frequency into the compliant range, using voltage control, temperature compensation, and frequency synthesis techniques to ensure specification adherence
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution ensures that the output clock signal accurately conforms to the specified frequency ppm range, thereby ensuring compliant data transmission, even when using low-cost, difficult-to-control clock generators, by automatically switching to a precise external clock signal when necessary.
Implementation Method 1
a phase locked loop (PLL) initially generates the output clock signal according to the first clock signal
Data Source
AI summary
A clock generation circuit for a transmitter which transmits data according to an output clock signal is provided. The clock generation circuit include a clock generator and a phase locked loop (PLL). The clock generator generates a first clock signal. The PLL initially generates the output clock signal according to the first clock signal. When a frequency of the output clock signal generated according to the first clock signal is not within a range required for specification of the transmitter, the PLL generates the output clock signal according to a second clock signal.