PLL Clock Switching with Synchronous Divider Restart
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Solution Overview
Problem
In telecommunication networks like SONET and SDH, switching between redundant input clocks often results in undesirable transients in the output clock due to phase differences and detection delays, which can lead to frequency and phase drifts, making hitless switching challenging.
Innovation Solution
A phase locked loop (PLL) system with a multiplexer, phase detector, filter block, oscillator, frequency divider, and clock switch controller that synchronously restarts the feedback divider and uses a delay block to lock onto delayed versions of input clocks, minimizing transients during switching by operating in a holdover mode and synchronously releasing the feedback divider from reset.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the system switches from one input clock to another input clock, then the system can maintain clock functionality and redundancy, but the output clock exhibits frequency and phase drift (transients) during the switching interval
Solution Approach 1:
The system pre-loads the secondary input clock into the PLL before switching occurs. When a switch is needed, the pre-loaded clock is already ready to immediately replace the primary clock without causing transients, as the phase and frequency information is already captured and prepared in advance
Solution Approach 2:
The patent introduces an intermediary mechanism (the dual-PLL architecture with pre-load capability) that mediates between the primary and secondary input clocks. This intermediary structure allows seamless transition by having the secondary PLL already synchronized to the standby clock, acting as a buffer that eliminates direct disruption to the output clock
2Measurement precision
If the system takes time to detect failure of the currently used input clock, then the detection accuracy is improved, but the switching interval increases causing longer transients in the output clock
Solution Approach 1:
The system continuously monitors both primary and secondary input clocks simultaneously using dual PLLs. This continuous monitoring of both clocks ensures that failure detection is immediate and accurate without requiring additional detection time, as both clocks are actively tracked and compared at all times
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables hitless switching between input clocks, reducing or eliminating transients in the output clock, thus maintaining phase and frequency lock with minimal disruption, even in the presence of phase differences and detection delays.
Implementation Method 1
A phase locked loop (PLL) system with a multiplexer, phase detector, filter block, oscillator, frequency divider, and clock switch controller that synchronously restarts the feedback divider and uses a delay block to lock onto delayed versions of input clocks
Data Source
AI summary
A phase locked loop (PLL) includes a multiplexer (MUX), a phase detector, a filter block, an oscillator, a frequency divider, and a clock switch controller, and achieves hitless switching between a primary clock and a redundant clock. The clock switch controller, upon detecting a condition requiring switching from the primary clock to the redundant clock, is operable to restart the feedback divider synchronously with respect to the redundant clock, and derive the output of the PLL from the redundant clock. The PLL further includes a delay block to process delayed phase error signals generated by the phase detector. The PLL performs hitless clock switching in the event of input clock loss or in response to a command to switch input clocks. The PLL further includes circuitry for estimating and cancelling residual phase errors.