PLL Reference Clock Switching with Controlled Frequency Drift
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional PLL circuits experience significant frequency glitches and phase errors during reference clock switching due to uncontrolled phase transitions between reference clocks with different frequencies and uncorrelated phases, failing to maintain output clock frequency within parts-per-million error and frequency change rate specifications.
Innovation Solution
The PLL circuit incorporates a reset controller to align the feedback clock with the newly selected reference clock, and a phase limit controller to limit phase error to a fixed value, ensuring smooth transitions by resetting the phase detector and frequency divider at the right time, and using a phase delay to maintain frequency stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If reference clock switching is performed in conventional PLL circuits, then the PLL can switch between multiple reference clocks with different frequencies, but large phase error and frequency glitch occur causing output frequency to exceed ppm error specifications
Solution Approach 1:
The patent applies preliminary action by resetting the phase detector and frequency divider before the actual reference clock switching occurs. The reset controller detects the switching event and asserts reset signals to clear the phase detector output and frequency divider state beforehand, ensuring that when the new reference clock is acquired, the phase error is minimized from the start rather than allowing large phase error to accumulate during transition.
Solution Approach 2:
The patent introduces a reset controller as an intermediary component that mediates between the reference clock switching event and the phase detector/frequency divider. This reset controller receives the reference clock select signal and generates coordinated reset signals to multiple circuit elements, acting as a control intermediary that ensures proper sequencing and minimizes phase error during the switching transition.
2Ease of operation
If reference clock switching is performed without phase control, then switching between reference clocks is simple, but phase difference between reference clocks translates to large phase error causing long transition time
Solution Approach 1:
The patent applies feedback by using the reference clock select signal as a trigger for the reset controller, which in turn generates reset signals back to the phase detector and frequency divider. This feedback mechanism ensures that the reset action is automatically triggered by the switching event itself, creating a closed-loop control that minimizes phase error without requiring complex external phase alignment circuitry.
3Device complexity
If conventional PLL switching is used, then circuit complexity is low, but frequency glitch causes output frequency to exceed ppm error and frequency change rate specifications
Solution Approach 1:
The reset controller performs preliminary resetting of the phase detector and frequency divider before the new reference clock stabilizes, preventing large phase error from developing during the transition. This preliminary action ensures that when the PLL locks to the new reference clock, the phase error is already minimized, keeping the output frequency within ppm error specifications without requiring complex frequency synthesis circuitry.
Data Source
AI summary
A reference clock switching controller for a PLL including select circuitry and a reset controller. The PLL includes a phase detector receiving a feedback clock and a selected reference clock, and a frequency divider receiving an output clock and providing the feedback clock. The select circuitry selects from among multiple reference clocks based on a select signal to provide the selected reference clock. The reset controller resets the phase detector in response to a transition of the select signal and releases the phase detector upon a following falling edge of the selected reference clock. The reset controller resets the frequency divider in response to the transition of the select signal and releases the frequency divider after the phase detector is released from reset upon a following rising edge of the selected reference clock. A phase limit controller limits phase error during clock switching by minimizing delay of feedback clock transitions.