PLL Reference Clock Switching with Controlled Frequency Drift
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Solution Overview
Problem
Conventional PLL circuits experience significant frequency glitches and phase errors during reference clock switching due to uncontrolled phase transitions between reference clocks with different frequencies and uncorrelated phases, failing to maintain output clock frequency within parts-per-million error and frequency change rate specifications.
Innovation Solution
A phase-locked loop (PLL) circuit with a reset controller that synchronizes the feedback clock with the newly selected reference clock by resetting the phase detector and frequency divider at specific edges of the reference clock transition, and optionally includes a phase limit controller to further reduce phase errors within a predefined limit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If reference clock switching is performed in conventional PLL circuits, then the PLL can switch between multiple reference clocks with different frequencies, but large phase error and frequency glitch occur during switching
Solution Approach 1:
The patent applies preliminary action by resetting the phase detector and frequency divider before the actual reference clock switching occurs. The reset controller detects the transition of the reference clock select signal and asserts reset signals to clear the phase detector and frequency divider beforehand, ensuring they start from a known state during switching, thus preventing large phase errors and frequency glitches
Solution Approach 2:
The patent uses feedback by monitoring the reference clock select signal transition and using this information to control the reset timing. The reset controller continuously observes the select signal and automatically triggers reset assertions when a transition is detected, creating a closed-loop control mechanism that adapts to switching events in real-time
2Ease of operation
If reference clock switching is performed without control, then switching between reference clocks is simple, but output clock frequency drifts significantly during transition
Solution Approach 1:
The patent introduces an intermediary component - the reset controller - that mediates between the reference clock select signal and the phase detector/frequency divider. This intermediary automatically manages the reset timing based on select signal transitions, providing controlled switching without requiring complex external control logic, thus maintaining both ease of operation and frequency stability
3Speed
If phase detector and frequency divider are reset at wrong timing, then switching speed is fast, but phase error increases and output frequency fails to meet specifications
Solution Approach 1:
The reset controller uses feedback from the reference clock select signal transition to determine the exact timing for asserting reset signals. By continuously monitoring the select signal and triggering reset assertions immediately upon detecting a transition, the system achieves both fast switching and precise phase error control
Solution Approach 2:
The reset controller asserts reset signals preliminarily upon detecting the select signal transition, before the phase detector and frequency divider would naturally accumulate significant phase error. This preliminary resetting ensures fast switching while maintaining phase accuracy by preventing error accumulation during the transition period
Data Source
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AI summary
A reference clock switching controller for a PLL including select circuitry and a reset controller. The PLL includes a phase detector receiving a feedback clock and a selected reference clock, and a frequency divider receiving an output clock and providing the feedback clock. The select circuitry selects from among multiple reference clocks based on a select signal to provide the selected reference clock. The reset controller resets the phase detector in response to a transition of the select signal and releases the phase detector upon a following falling edge of the selected reference clock. The reset controller resets the frequency divider in response to the transition of the select signal and releases the frequency divider after the phase detector is released from reset upon a following rising edge of the selected reference clock. A phase limit controller limits phase error during clock switching by minimizing delay of feedback clock transitions.