PLL Clock Source Switching for Lower Wireless Interference
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Solution Overview
Problem
Modern electronic devices face interference issues in wireless communication channels due to clocking signals, which are exacerbated by the need to switch between different communication channels and standards, making it challenging to find a single 'safe' frequency for the clock source.
Innovation Solution
A system and method that adjusts the phase locked loop (PLL) clock source by switching from a static clock to a modulated or programmable clock, aligning the latter using a phase detector and counter to prevent loss of lock, and utilizing a spread spectrum clock to mitigate interference by constantly modulating the frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a static clock is used during device initialization, then the device can operate during boot up, but wireless communication interference occurs and loss of lock may occur when switching clocks
Solution Approach 1:
The patent applies dynamics by transitioning from a static clock source to a dynamic/programmable clock source that can adjust its frequency. The programmable clock allows the system to change clock frequencies based on operational requirements, thereby reducing wireless communication interference while maintaining reliable operation during initialization and switching.
Solution Approach 2:
The patent implements parameter changes by modifying the clock frequency parameter. A programmable clock source is used that can change its operating frequency to avoid interfering with wireless communication channels. The system adjusts clock frequency parameters dynamically to eliminate interference while maintaining system functionality.
2Object-affected harmful factors
If a modulated or programmable clock is used to reduce interference, then wireless communication interference is reduced, but the clock may not be available during initialization and alignment complexity increases
Solution Approach 1:
The patent introduces an intermediary alignment mechanism between the static and programmable clock sources. This intermediary system includes circuitry and methods that automatically align the phase and frequency of the programmable clock with the static clock, thereby reducing interference complexity and simplifying the transition process.
Solution Approach 2:
The patent applies preliminary action by performing clock alignment procedures before the programmable clock becomes fully operational. The system prepares the clock switching mechanism in advance, ensuring that when the programmable clock is activated, it is already aligned with the static clock, preventing loss of lock and reducing operational complexity.
3Object-affected harmful factors
If clock frequency is changed to avoid interference, then wireless communication channels are protected, but loss of lock occurs during transition from first clock to second clock
Solution Approach 1:
The patent implements beforehand cushioning by preparing the PLL and clock switching mechanism in advance to prevent loss of lock. The system includes alignment circuitry and control methods that ensure the programmable clock is pre-synchronized with the static clock before switching, providing a cushion against potential lock loss during frequency transitions.
Solution Approach 2:
The patent employs feedback mechanisms to monitor PLL lock status during clock transitions. The system uses feedback from the PLL to detect potential loss of lock conditions and adjusts the clock switching timing and parameters accordingly, ensuring stable transitions while changing clock frequencies to avoid wireless communication interference.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively reduces wireless communication interference by aligning and switching clock signals, ensuring continuous operation without losing lock, even when switching between different wireless communication channels.
Implementation Method 1
The phase detector may detect whether the two clocks are aligned. If they are not aligned, the phase detector may modify the counter (e.g., either up or down) based on the difference in phase
Data Source
AI summary
Adjusting a phase locked loop (PLL) clock source to reduce wireless communication (e.g., radio frequency (RF)) interference within a device. The PLL may be included in a high speed serial interface, e.g., coupled to a display, and may be initially driven by a first clock. Later, when a second clock is available and aligned with the first clock, the PLL may be driven by the second clock. The second clock may be configured to change its frequency over time such that the PLL does not lose lock and also does not interfere (or reduces interference) with wireless communication of the device. For example, the second clock may be programmable or may dynamically vary its operating frequency, thereby reducing its interference with the wireless communication of the device.