PLL Reference Clock Switching With TDC Phase Cancellation
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Solution Overview
Problem
Phase-locked loops (PLLs) experience sudden frequency and phase shifts when switching between multiple reference clocks, disrupting operations, such as packet corruption or dropout in communication transceivers.
Innovation Solution
Incorporating a multiplexer with multiple reference clock inputs, a time-to-digital converter (TDC), an averager circuit, and a digital loop filter, where the frequency control word is temporarily frozen upon switching, and the TDC averages new values to maintain a stable output clock frequency and phase by subtracting the average value from newly generated TDC outputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a multiplexer switches between multiple reference clocks, then the PLL can adapt to different reference sources, but sudden frequency and phase shifts occur disrupting operation
Solution Approach 1:
The system performs preliminary actions by freezing the frequency control word before switching reference clocks and calculating the phase difference in advance. The TDC measures the phase offset between the old and new reference clocks, and this measurement is used to pre-calculate compensation values that will be applied after switching, preventing sudden disruptions.
Solution Approach 2:
The system implements feedback by continuously monitoring the phase difference between reference clocks using the TDC. The measured phase offset is fed back to the digital loop filter, which generates compensating frequency control words that adjust the VCO output to maintain phase lock despite reference clock changes.
2Stability of the object's composition
If the frequency control word is frozen during reference clock switching, then phase lock is maintained, but the digital loop filter must dynamically generate new frequency control words after switching
Solution Approach 1:
The digital loop filter performs preliminary calculations before switching by computing the expected frequency control words based on the measured phase offset. These pre-calculated values are stored and then applied after switching, simplifying the post-switching operation and maintaining stability without requiring complex real-time adjustments.
Solution Approach 2:
The system introduces an intermediary mechanism by using the TDC phase measurement as a mediator between the reference clock switch and the frequency control word generation. This intermediary measurement allows the digital loop filter to generate appropriate frequency control words without directly reacting to the abrupt clock switch, smoothing the transition.
3Stability of the object's composition
If the TDC averages new output values after switching, then the average value stabilizes the output, but additional processing time is required
Solution Approach 1:
The system applies partial averaging by computing the average of only the necessary number of TDC output values required to achieve sufficient stabilization. Rather than continuously averaging all possible measurements, the system performs a limited number of averaging operations that provide adequate stability while minimizing the time penalty.
Solution Approach 2:
The averaging process is performed as a preliminary action immediately after reference clock switching, establishing a stable baseline phase measurement before normal operation resumes. This preliminary averaging prevents subsequent instability without requiring ongoing time-consuming calculations during normal phase-locked operation.
Data Source
AI summary
A phase-locked loop (PLL) including a multiplexer with multiple inputs, each input coupled to receive a different reference clock. A time-to-digital converter (TDC) generates a TDC output value based on a phase difference between a reference clock from the multiplexer and a feedback clock. An averager circuit coupled to an output of the TDC. An adder circuit is coupled to outputs of the TDC and the averager circuit. A loop filter is coupled to an output of the adder circuit.