PLL Reference Clock Switching With Reduced Frequency Fluctuation
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Solution Overview
Problem
Existing PLL circuits experience frequency fluctuation during reference clock signal switching, which is not adequately addressed by prior technologies, particularly in applications requiring low frequency fluctuation such as the USB4 standard.
Innovation Solution
A PLL circuit with a selection circuit and control circuit that temporarily reduces the division ratio of the frequency divider during reference clock signal switching, and masks detection results from the phase comparator to synchronize the feedback clock signal with the reference clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a PLL circuit switches a reference clock signal using a conventional configuration, then the circuit can change clock sources, but phase shift and frequency fluctuation occur during switching
Solution Approach 1:
The control circuit performs preliminary actions by resetting the frequency divider and temporarily reducing the division ratio before the reference clock signal switching is complete. This preparatory adjustment ensures that the feedback clock signal can quickly adapt to the new reference clock frequency, preventing phase shift and frequency fluctuation during the transition.
Solution Approach 2:
The invention dynamically changes the division ratio parameter of the frequency divider during reference clock signal switching. By temporarily reducing the division ratio, the feedback clock signal frequency is adjusted to match the new reference clock frequency, thereby maintaining frequency stability during the switching process.
2Reliability
If the division ratio is temporarily reduced during reference clock signal switching, then frequency fluctuation is inhibited, but the control circuit complexity increases
Solution Approach 1:
The control circuit uses feedback from the phase comparator to detect phase differences between the reference clock signal and feedback clock signal. Based on this feedback, the control circuit automatically adjusts the division ratio of the frequency divider, creating a closed-loop control system that maintains frequency stability without requiring complex external control mechanisms.
3Stability of the object's composition
If phase comparator detection results are masked during switching, then synchronization is improved, but the response time increases
Solution Approach 1:
The control circuit periodically masks the phase comparator detection results at specific intervals during the reference clock signal switching process. This periodic masking allows the frequency divider to complete its reset and division ratio adjustment without interference from phase comparison, ensuring proper synchronization while minimizing the masking duration to maintain fast response time.
Data Source
AI summary
A phase-locked loop (PLL) circuit generates an output clock signal and includes: a selection circuit that selects one of a plurality of clock signals as a reference clock signal of the PLL circuit; and a control circuit that when a switch is made for the selection of the reference clock signal, temporarily reduces a division ratio used by a frequency divider that generates a feedback clock signal to be compared with the reference clock signal.