PLL Clock Switchover Circuit With Pre-Aligned Backup Phase Tracking
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Solution Overview
Problem
Conventional phase lock loops (PLL) fail to distinguish input frequency changes, leading to incorrect phase lock and erroneous communication, and switching between redundant input clock signals takes a lengthy duration, causing discontinuities in interface bit rate.
Innovation Solution
A circuit and method utilizing a phase frequency detector to detect phase shifts, combined with coarse and fine tuning mechanisms, including delay elements, inverters, latches, and logic gates, to align the feedback clock signal with a backup reference clock signal, reducing the switchover time to a single delay element duration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional phase lock indicators are used to detect loss of phase lock, then the system can identify when the input clock signal becomes invalid, but the system cannot distinguish input frequency changes and the PLL locks to incorrect frequencies
Solution Approach 1:
The phase detector function is segmented into two independent components: a phase detector that only detects phase differences and a frequency detector that specifically detects frequency changes. This segmentation allows the system to distinguish between phase lock status and frequency matching status, resolving the contradiction by enabling both reliable phase lock detection and precise input frequency distinction through separate detection mechanisms.
2Reliability
If redundant input clock signals are applied to the phase lock loop, then the system can switch to a backup signal when the primary signal becomes invalid, but the switchover takes a lengthy duration of 156 picoseconds causing discontinuities
Solution Approach 1:
The feedback clock signal is preliminarily aligned with the backup reference clock signal before a switchover is actually needed. By continuously maintaining phase alignment between the feedback signal and both primary and backup reference signals, the system prepares the backup path in advance, so that when a switchover is triggered, the transition time is dramatically reduced from 156 picoseconds to just 19 picoseconds, eliminating operational discontinuities.
3Speed
If the feedback clock signal is directly switched to the backup reference clock signal, then the switchover can occur quickly, but phase misalignment causes tracking difficulties and discontinuities with the interface bit rate
Solution Approach 1:
A phase alignment mechanism using feedback is implemented where the phase detector continuously monitors the phase difference between the feedback clock signal and the backup reference clock signal. The system adjusts the feedback signal phase based on this detection to maintain alignment, ensuring that when switchover occurs, both speed and phase stability are preserved, eliminating tracking difficulties and interface bit rate discontinuities.
4Adaptability or versatility
If the PLL attempts to re-achieve phase lock when the input clock frequency changes, then the output signal follows the frequency change, but the phase lock indicator incorrectly reports valid phase lock status
Solution Approach 1:
The detection system is segmented into separate phase detection and frequency detection functions. The phase detector identifies when phase lock is actually achieved, while the frequency detector specifically identifies frequency changes. By combining these segmented detection capabilities, the system can accurately determine both frequency tracking status and true phase lock status, preventing incorrect validation reports when frequency changes occur.
Data Source
AI summary
A circuit for reducing a time to switch between the redundant clock signals applied to a phase lock loop. The circuit includes a phase frequency detector of the phase lock loop that detects a shift in the phase of a reference clock signal relative to the phase of a feedback clock signal. The circuit further includes a coarse tuning mechanism configured to delay the feedback clock signal until the feedback clock signal is aligned with a backup reference clock signal. Furthermore, the circuit includes a fine tuning mechanism configured to align the edge of the feedback clock signal with the edge of the backup reference clock signal, such as by utilizing a series of delay elements to delay the backup reference clock signal at different points in time and selecting the appropriate delayed backup reference clock signal whose edge is aligned with the edge of the feedback clock signal.