PLL Clock Synchronization Across Multi-Die Network Ports
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Solution Overview
Problem
Current clock synchronization methods in network devices face challenges such as inaccurate latency measurements due to unsynchronized clocks, increased complexity with larger integrated circuits, and the introduction of noise and jitter, especially in devices with multiple dies and ports.
Innovation Solution
A network device with frequency generation circuitry that includes a phase-locked loop (PLL) and receivers to recover remote clocks, a controller to identify the master clock and adjust the local clock iteratively to match it, and a closed feedback loop with a frequency mixer to reduce clock differential, thereby simplifying synchronization and minimizing noise and jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If recovered clocks are multiplexed throughout the network device, then clock synchronization is achieved, but noise and jitter are introduced
Solution Approach 1:
The patent divides the network device into multiple segments, each with its own local clock source. Instead of multiplexing a single recovered clock throughout the entire device, each segment generates and uses its own local clock, eliminating the noise and jitter associated with clock multiplexing while maintaining synchronization through the PLL control mechanism
Solution Approach 2:
The patent changes the frequency parameter of local clocks to match the master clock frequency. By using PLLs to adjust the frequency of local clocks based on feedback from the master clock, the system achieves synchronization without physically multiplexing clocks, thereby avoiding noise and jitter introduction
2Reliability
If multiple recovered clocks are multiplexed in devices with multiple dies, then clock alignment is achieved, but complexity increases
Solution Approach 1:
The patent merges the clock generation function into each die by providing frequency generation circuitry on each die. This eliminates the need for complex clock multiplexing across multiple dies, as each die independently generates its own clock while the PLL ensures alignment with the master clock, thereby reducing overall system complexity
3Reliability
If a single master clock is used throughout the network device, then synchronization is achieved, but noise and jitter propagate
Solution Approach 1:
The patent introduces local PLLs as intermediaries between the master clock and the actual clock usage in each segment. The PLL acts as a buffer that receives the master clock signal and generates a clean local clock, preventing direct propagation of noise and jitter from the master clock while maintaining synchronization
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables accurate clock synchronization across network devices without multiplexing recovered clocks, reducing noise and jitter, and scaling effectively for devices with multiple dies and ports, ensuring precise clock alignment and improved latency measurements.
Implementation Method 1
a phase-locked loop (PLL) configured to generate a local clock based on the clock signal
Implementation Method 2
a frequency mixer configured to combine the control signal from the controller with an output of the switching circuitry to generate the clock signal as a combined signal
Data Source
AI summary
In one embodiment, a network device includes frequency generation circuitry configured to generate a clock signal, a phase-locked loop (PLL) configured to generate a local clock based on the clock signal, a plurality of receivers configured to receive respective data streams from respective remote clock sources, each receiver of the plurality of receivers being configured to recover a remote clock from a respective data stream, and a controller configured to identify the remote clock recovered by one of the plurality of receivers as a master clock, find a clock differential between the identified remote clock and the local clock, and provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuitry to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential.