PLL Clock Window Detection for Early and Late Reference Edges
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Solution Overview
Problem
Phase-locked loops (PLLs) face challenges in detecting early and late reference clock edges, which can impair their performance due to jitter or other frequency variations, as existing systems can only effectively detect late or missing clocks, not early clocks.
Innovation Solution
A circuit comprising a selection circuit, a phase-locked loop, and reference clock window detector circuits that utilize early and late time windows to detect both early and late reference clock edges, asserting an error signal to a finite state machine for corrective action, allowing the system to switch to a different reference clock if an error is detected.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing clock detection methods are used, then late or missing clocks can be detected, but early clocks cannot be detected
Solution Approach 1:
The detection window is segmented into multiple regions: an early window before the expected clock edge, a valid window during the expected edge arrival, and a late window after the expected edge. This segmentation allows the circuit to distinguish between early,准时, and late clock edges by determining which segment the actual edge falls into, thereby achieving comprehensive detection capability that overcomes the limitation of detecting only late or missing clocks.
2Reliability
If reference clock frequency varies due to jitter, then phase perturbation occurs on PLL output clock, but detection and correction is delayed
Solution Approach 1:
The circuit performs preliminary detection by establishing early and late detection windows in advance of the expected reference clock edge. These windows are prepared beforehand based on the nominal clock period, allowing the circuit to immediately detect phase perturbations when they occur without waiting for the nominal edge arrival time, thus reducing detection response time and enabling faster correction of frequency variations.
Solution Approach 2:
The circuit generates error signals based on detected clock edge timing relative to the defined windows, and these error signals are fed back to control the PLL to correct phase perturbations. This feedback mechanism continuously monitors and corrects frequency variations, maintaining output clock stability by rapidly responding to detected errors and adjusting the PLL accordingly.
Data Source
AI summary
A selection circuit receives a plurality of reference clocks. The selection circuit is controlled by a control signal to output one of the plurality of reference clocks. A phase-locked loop couples to an output of the selection circuit and uses the selected reference clock for phase locking an output clock. A plurality of reference clock window detector circuits is included. Each reference clock window detector circuit receives a separate reference clock. Each reference clock window detector circuit asserts an error signal responsive to an early reference clock edge error in which the reference clock window detector circuit detects a reference clock edge before expiration of an early time window. Further, each reference clock window detector circuit asserts the error signal responsive to a late reference clock edge error in which the reference clock window detector circuit detects a reference clock edge after expiration of a late time window.