PLL Reference Clock Switching With Zero-Phase Relock
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Solution Overview
Problem
Conventional PLL systems face challenges in minimizing output frequency changes during the hold state and implementing zero phase start (ZPS) upon relock, requiring significant calculations, power consumption, and additional circuitry, which leads to poor performance during dynamic switching between high and low frequency reference input clocks.
Innovation Solution
The proposed PLL system incorporates an active loop filter with strategically placed switches to eliminate charge leakage paths during the hold state and digital synchronizing circuitry that synchronizes the rising edges of the reference and feedback inputs upon relock, achieving ZPS without the need for complex calculations or additional computational resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional PLL systems implement ZPS upon relock through complex calculations and additional circuitry, then phase errors are reduced, but power consumption increases and silicon space requirements increase
Solution Approach 1:
The patent extracts and eliminates the complex calculation circuits and additional computational resources from the PLL system. Instead of using conventional ZPS implementation with heavy computational burden, the invention uses a simplified approach where the charge pump is directly controlled to source or sink charge based on divider output transitions, removing the need for complex calculations and reducing power consumption while maintaining phase error reduction
Solution Approach 2:
The patent implements self-service by using the PLL system's own existing components (charge pump, dividers, phase detector) in a coordinated manner to achieve ZPS functionality. The charge pump responds directly to divider output transitions without external control signals or additional circuitry, allowing the system to self-correct phase errors using its inherent components, thereby reducing the need for additional power-consuming circuits
2Measurement precision
If conventional PLL systems implement ZPS upon relock through complex calculations and additional circuitry, then phase errors are reduced, but device complexity increases
Solution Approach 1:
The patent removes complex calculation circuits and additional computational resources from the PLL system. The invention replaces conventional ZPS implementation with a simplified method that uses only the existing charge pump and divider components, eliminating the need for complex control logic and reducing device complexity while maintaining phase error reduction capability
Solution Approach 2:
The patent makes existing components perform multiple functions. The charge pump not only maintains its primary function of charging/discharging the loop filter capacitor but also directly responds to divider output transitions to implement ZPS. This multi-functionality eliminates the need for separate ZPS control circuits, reducing overall device complexity
3Stability of the object's composition
If the PLL holds the present VCO frequency during crystal oscillator switching, then output frequency stability is maintained, but large phase errors arise causing large temporary frequency glitches upon relock
Solution Approach 1:
The patent applies preliminary action by preparing the charge pump to source or sink charge in advance based on the transition of divider outputs. When the PLL exits hold mode, the charge pump is already positioned to correct phase errors immediately, preventing large temporary frequency glitches while maintaining output frequency stability during the hold period
Solution Approach 2:
The patent uses feedback by monitoring the transitions of divider outputs and using this information to control the charge pump's operation. The charge pump responds to the phase relationship between reference and feedback signals by detecting divider output transitions, creating a feedback mechanism that automatically corrects phase errors upon relock without causing frequency glitches
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes frequency changes during the hold period, reduces phase errors, and enables fast relock times, maintaining output stability with reduced power consumption and silicon space requirements.
Implementation Method 1
a voltage controlled oscillator portion arranged to output an output signal based on the tuning signal
Data Source
AI summary
A circuit is provided for use with a clock having an input divider portion, a feedback divider portion, a phase detector portion, a loop compensation filter portion and a voltage controlled oscillator portion. The input divider portion receives a reference signal and outputs a divided reference signal. The feedback divider portion receives an output signal from the circuit and outputs a divided feedback signal. The phase detector portion outputs a phase detector signal based on the divided reference signal and the divided feedback signal. The loop compensation filter portion outputs a tuning signal based on the phase detector signal. The voltage controlled oscillator portion output the outputs a signal based on the tuning signal. The phase detector portion changes the phase detector signal based on the input divider portion receiving the control signal and the feedback divider portion receiving the control signal.