Programmable PLL Clocking for Multi-Protocol Transceiver Channels
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Solution Overview
Problem
Current multi-channel, multi-protocol transceivers require multiple reference clocks, leading to increased system cost, silicon area occupation, susceptibility to crosstalk and noise, and difficulty in scaling to accommodate more channels and protocols, due to the need for separate reference clock sources operating at different frequencies.
Innovation Solution
A programmable phase lock loop system that generates multiple output clock frequencies from a single constant reference clock frequency using a multiplexer, integer dividers, and a voltage-controlled oscillator, allowing for independent channel configuration and protocol adaptation without the need for separate reference clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple reference clocks are used for multi-channel multi-protocol transceivers, then each channel can operate at its required frequency, but system cost and silicon area increase
Solution Approach 1:
A single reference clock source is designed to serve multiple channels and protocols simultaneously. The reference clock distribution network routes the same clock signal to multiple phase-locked loops, each configured for different protocols through programmable dividers and frequency synthesis, eliminating the need for separate reference clocks for each channel.
Solution Approach 2:
Multiple reference clock sources are merged into a single shared reference clock. The system combines the functions of what would traditionally require separate clock sources by using one high-quality reference clock that is distributed and synthesized to meet the frequency requirements of multiple channels through programmable frequency division and multiplication.
2Adaptability or versatility
If multiple reference clocks are used, then each channel can operate independently, but susceptibility to crosstalk and noise increases
Solution Approach 1:
Multiple reference clock sources are merged into a single shared reference clock, which inherently reduces crosstalk and noise issues associated with having multiple separate clock sources. The single reference clock is distributed through a controlled network with proper isolation and buffering to maintain signal integrity across multiple channels.
3Adaptability or versatility
If separate reference clock sources are used for different frequencies, then protocol-specific frequency requirements are met, but device complexity increases
Solution Approach 1:
A universal reference clock distribution network is designed that can accommodate multiple frequency requirements through programmable frequency synthesis. The system uses a single reference clock that can be divided and multiplied to generate the appropriate frequencies for different protocols, controlled through programmable dividers and synthesizers in each channel.
Solution Approach 2:
The system employs programmable and reconfigurable frequency synthesis elements that can dynamically adjust to different protocol requirements. The dividers and frequency multipliers are controlled by configuration registers that allow the same hardware to adapt to different frequency needs without physical reconfiguration.
4Adaptability or versatility
If multiple reference clocks are used, then each channel can be optimized for its protocol, but scalability to more channels becomes difficult
Solution Approach 1:
The reference clock system is designed as a universal platform that can support an arbitrary number of channels through replication of the phase-locked loop and frequency synthesis blocks. Each channel receives the same reference clock and independently synthesizes its required frequency, allowing easy scaling by adding more identical channel blocks without adding more reference clock sources.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces system cost and silicon area, minimizes crosstalk, and enables easy scalability to support multiple channels and protocols, while maintaining optimal clock jitter performance and flexibility.
Implementation Method 1
A programmable phase lock loop system that generates multiple output clock frequencies from a single constant reference clock frequency
Implementation Method 2
the one of the plurality of output clock frequencies being produced based on: the routing of the multiplexer, the divisor of the first integer divider, and the divisor of the second integer divider
Data Source
AI summary
A circuit for producing one of a plurality of output clock frequencies from a single, constant input reference clock frequency. The circuit comprises a reference clock system and a phase lock loop. The reference clock system includes a bypass path, a divider path including a first integer divider, and a multiplexer. A divisor of the first integer divider is based on a selected communications protocol of a group of possible communications protocols. The multiplexer is configured to route the bypass path or the divider path based on the selected communications protocol. The phase lock loop includes a voltage controlled oscillator and a feedback path. The feedback path includes a second integer divider. A divisor of the second integer divider is based on the selected communications protocol. The reference clock system is configured to receive a constant reference clock frequency. The voltage controlled oscillator is configured to produce one of a plurality of output clock frequencies corresponding to the selected communications protocol. The selected output clock frequency is produced based on at least one of the routing of the multiplexer, the divisor of the first integer divider, and the divisor of the second integer divider.