PLL Frequency Calibration Using Coarse-Fine Capacitor Tuning
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing frequency calibration techniques for voltage controlled oscillators in phase locked loops result in long calibration times due to the need for numerous comparisons, particularly when using N-bit wide switched capacitor arrays with 2:1 weight ratios, leading to increased calibration times as N increases.
Innovation Solution
A phase locked loop frequency calibration circuit and method that includes a timer, counter, control module, and frequency divider, where the control module clears and controls the counter to count output clock signals within a preset time, calculates the output frequency, compares it to an expected frequency, and adjusts the number of switched capacitors to align the output frequency, thereby reducing calibration time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If successive comparison calibration algorithm is used with N-bit wide switched capacitor array, then frequency calibration accuracy is improved, but calibration time increases significantly
Solution Approach 1:
The patent segments the N-bit calibration process into two distinct phases: a fast coarse calibration phase that handles the most significant bits (MSBs) using a simplified algorithm, and a fine calibration phase that handles the least significant bits (LSBs) with higher precision requirements. This segmentation allows the system to achieve both fast initial convergence and high final accuracy, resolving the contradiction between calibration speed and precision.
Solution Approach 2:
The patent implements preliminary coarse calibration before fine calibration. The coarse calibration phase pre-adjusts the VCO frequency by calibrating the MSBs first, bringing the frequency close to the target value. This preliminary action reduces the range for subsequent fine calibration, significantly reducing the total calibration time while maintaining high accuracy.
2Manufacturing precision
If N-bit wide switched capacitor array with 2:1 weight ratio is used, then frequency resolution is improved, but number of comparisons increases exponentially
Solution Approach 1:
The patent divides the N-bit capacitor array calibration into two segments: coarse calibration for MSBs and fine calibration for LSBs. Each segment uses an optimized comparison algorithm appropriate to its precision requirements, reducing the total number of comparisons from exponential O(2^N) to a manageable linear or near-linear complexity while preserving the fine frequency resolution provided by the full N-bit array.
Solution Approach 2:
The patent applies partial action by performing sufficient but not excessive comparisons. In the coarse calibration phase, it performs enough comparisons to bring the frequency within an acceptable range, then transitions to fine calibration which performs a limited number of additional comparisons to achieve final precision. This avoids the excessive comparisons that would be required if all N bits were calibrated with full precision algorithms.
3Measurement precision
If full precision calibration algorithm is applied to all bits, then calibration accuracy is improved, but calibration time becomes unacceptably long
Solution Approach 1:
The patent segments the calibration algorithm into two distinct precision levels: coarse calibration for MSBs with lower precision requirements and faster convergence, and fine calibration for LSBs with higher precision requirements. This segmentation allows the system to apply appropriate precision to each bit group, achieving high overall accuracy without the excessive time cost of applying full precision algorithms to all bits.
Solution Approach 2:
The patent performs preliminary coarse calibration on MSBs before fine calibration on LSBs. This preliminary action establishes a good initial frequency estimate that reduces the calibration range for subsequent fine calibration, enabling the system to achieve high overall accuracy in fewer total iterations and thus improving calibration speed.
Data Source
AI summary
A phase locked loop frequency calibration circuit and a method are provided. The circuit includes a timer, a counter, a control module, a frequency divider and a voltage controlled oscillator; output of voltage controlled oscillator is connected with first input of frequency divider, output of frequency divider is connected with first input of counter, second input of frequency divider, first input of timer and second input of counter are respectively connected with first output of control module, third input of counter is connected with output of timer, output of counter is connected with first input of control module, a reference clock signal is respectively sent to second input of timer and second input of control module, the number of clocks used by frequency divider to perform frequency division on output clock signal of voltage controlled oscillator is sent to third input of control module.