Phase-Locked Loop with Coarse-Fine Control for Low-Jitter Sync
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Solution Overview
Problem
Existing phase-locked loops face challenges in generating high-quality clock signals, particularly in communication systems, where maintaining synchronization and reducing jitter is crucial for reliable data transmission.
Innovation Solution
A phase-locked loop configuration that includes a detector, oscillator, adjuster, and controller, utilizing a variable delay circuit and gated VCO oscillation circuit to adjust phase and frequency differences, ensuring synchronization and reducing jitter through precise control of delay and frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional phase-locked loop is used to generate a clock signal, then the basic synchronization function is achieved, but the clock signal quality (low jitter) is not sufficient
Solution Approach 1:
The PLL is divided into two independent control loops: a coarse control loop using a frequency divider to handle large frequency deviations, and a fine control loop using a variable delay circuit to handle small phase adjustments. This segmentation allows each loop to be optimized for its specific function, improving overall clock signal quality without requiring a single complex loop to handle all scenarios
Solution Approach 2:
The system dynamically switches between coarse and fine control modes based on the frequency deviation magnitude. The frequency divider is activated when large deviations occur, while the variable delay circuit takes over for precise phase alignment. This dynamic adaptation enables the PLL to maintain low jitter across varying operating conditions while keeping the control structure manageable
2Adaptability or versatility
If the phase and frequency control ranges are increased to handle larger deviations, then the adaptability is improved, but the jitter of the clock signal increases
Solution Approach 1:
The control range is segmented into two zones: a wide coarse control zone handled by the frequency divider for large frequency deviations, and a narrow fine control zone handled by the variable delay circuit for small phase adjustments. This segmentation allows the system to maintain high adaptability across different operating conditions while keeping jitter low in the critical fine control zone
Solution Approach 2:
The system dynamically selects the appropriate control mechanism based on the magnitude of frequency deviation. When deviations are large, the frequency divider provides broad adaptability; when deviations are small, the variable delay circuit provides precise control with minimal jitter. This dynamic selection resolves the contradiction between wide control range and low jitter
3Adaptability or versatility
If a frequency divider is used to expand the control range, then the adaptability is improved, but the jitter of the generated clock signal increases
Solution Approach 1:
The control function is segmented between the frequency divider and variable delay circuit based on the magnitude of required adjustment. The frequency divider handles coarse frequency alignment to establish basic synchronization and expand control range, while the variable delay circuit handles fine phase adjustment to minimize jitter in the final clock signal
Solution Approach 2:
The system dynamically transitions from frequency divider-based coarse control to variable delay circuit-based fine control as the frequency deviation decreases. This dynamic progression allows the frequency divider to provide wide adaptability without permanently degrading jitter, as the variable delay circuit takes over for precise jitter reduction in the locked state
Data Source
AI summary
A phase-locked loop of the disclosure includes a detector, an oscillator, an adjuster, and a controller. The detector detects a transition of an input clock signal. The oscillator generates a clock signal having a frequency corresponding to a first control signal, and changes a phase of the clock signal on a basis of a detection result in the detector. The adjuster adjusts a phase difference between a phase of the input clock signal and the phase of the clock signal depending on a second control signal. The controller compares the phase of the input clock signal and the phase of the clock signal at a plurality of comparison timings, and generates the first control signal and the second control signal on a basis of a result of the comparison.