PLL Loop Filter Coarse-Fine Tuning for Fast Lock and Low Phase Noise
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Solution Overview
Problem
Existing PLL designs face challenges in reducing tuning time without introducing excess noise, particularly with VCOs having large voltage ranges, and existing coarse tune circuits are expensive and vulnerable to phase noise.
Innovation Solution
A PLL filter circuit that combines fine and coarse tune signals using summing elements and a smoothing filter, with a voltage divider and elliptical filter to reduce noise and sensitivity, allowing for faster tuning with reduced phase noise and spur attenuation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If fast tuning is implemented by increasing voltage slew, then tuning time is reduced, but phase noise and spurs increase
Solution Approach 1:
The patent segments the tuning process into two distinct parts: a coarse tuning stage that provides large voltage changes for fast frequency jumps, and a fine tuning stage that provides small voltage changes for precise frequency adjustment. This segmentation allows each stage to operate in its optimal noise regime, with the coarse stage completing quickly and the fine stage settling with low noise.
Solution Approach 2:
The patent applies preliminary action by performing coarse tuning first to rapidly establish the target frequency, then transitioning to fine tuning to achieve the final precise frequency. This preliminary coarse adjustment reduces the burden on the fine tuning stage, allowing it to settle with minimal noise and spurs.
2Speed
If existing coarse tune circuits are used to improve tuning speed, then voltage slew is increased, but device complexity and cost increase due to additional circuitry
Solution Approach 1:
The patent makes the single VCO tune line serve dual purposes: it receives fine tuning voltage from the PLL loop filter for normal operation, and it receives coarse tuning voltage from an external source when fast frequency changes are needed. This multi-functionality eliminates the need for separate coarse and fine tune lines, reducing circuit complexity while maintaining fast tuning capability.
3Loss of time
If existing coarse tune circuits are used to reduce tuning time, then voltage slew is increased, but phase noise is introduced on the VCO tune line
Solution Approach 1:
The patent segments the tuning voltage generation into two separate sources that are summed at the VCO tune line: a clean fine tuning voltage from the PLL loop filter and a coarse tuning voltage from an external source. The summation is designed so that the coarse voltage is applied only during frequency transitions and then removed, allowing the clean fine tuning voltage to dominate during steady-state operation, thus minimizing phase noise.
Solution Approach 2:
The patent implements periodic action by applying coarse tuning voltage only during the brief period when frequency changes are needed, then removing it once the transition is complete. This time-limited application of coarse voltage minimizes its impact on phase noise while still achieving fast tuning during the transition period.
Data Source
AI summary
A loop filter for a phase locked loop (PLL) having fast tuning capability while limiting phase noise. The filter includes a fine tune input port to receive a fine tune signal from the phase detector and a coarse tune input port to receive a coarse tune signal from the coarse tuner. The external coarse tuner provides the majority of the voltage slew on the loop filter while a fine tune control, thus reducing tune time. In one embodiment, the loop filter includes a voltage divider to limit the effective tuning sensitivity and thus control noise induced on a voltage-controlled oscillator from the loop filter. An elliptical filter may be employed to attenuate fractional spurs within the filter output signal.