PLL Reference Loss Detection with Feedback-Shifted Code Comparison
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Solution Overview
Problem
Existing PLL clock generation systems fail to promptly detect the loss of an input reference signal, leading to system malfunctions and data loss due to delayed detection and increased noise from ratiometric comparisons and separate clock domains.
Innovation Solution
A code-based loss detector system that generates unique codes each clock cycle using a pseudo-random number generator, with a PLL-derived clock shifting codes through serial registers, allowing for early detection of input reference signal loss by comparing register values, reducing false positives and enabling swift mitigation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ratiometric comparison with separate clock generator is used for reference loss detection, then detection capability is provided, but detection delay increases and circuit complexity increases
Solution Approach 1:
The patent combines the reference loss detection function with the existing PLL circuit by using the same feedback clock signal for both PLL operation and loss detection. The code generator and serial registers are integrated into the PLL structure, eliminating the need for separate clock generators and ratiometric comparison circuits. This merging reduces circuit complexity and enables faster detection since the detection process uses the same clock domain without requiring additional clock synchronization.
2Reliability
If ratiometric comparison with separate clock generator is used for reference loss detection, then detection capability is provided, but circuit complexity and noise increase
Solution Approach 1:
The patent integrates the loss detection functionality within the existing PLL circuit structure. The code generator produces codes synchronized to the feedback clock, and serial registers store and compare these codes using the same clock domain. This eliminates the need for separate clock generators, counter circuits, and complex ratiometric comparison logic, thereby reducing overall circuit complexity while maintaining detection capability.
Solution Approach 2:
The patent extracts the essential detection function from complex ratiometric comparison circuits and implements it using a simplified code generation and comparison mechanism. By using a code generator that produces unique codes for each feedback clock cycle and comparing stored codes in serial registers, the system achieves reference loss detection without requiring the complex infrastructure of separate clock domains and ratio-based detection algorithms.
3Speed
If code-based loss detector with PLL-derived clock is used, then detection speed improves and noise is reduced, but implementation complexity increases
Solution Approach 1:
The system uses its own feedback clock signal to drive the code generator and clock the serial registers for code comparison. This self-service approach eliminates the need for external separate clock sources and simplifies the implementation. The feedback clock, which is already present in the PLL circuit, is reused to generate detection codes and perform comparisons, thereby achieving fast detection without adding significant implementation complexity.
Data Source
AI summary
In described examples, a first clock generator generates an output clock signal in response to an input reference signal and in response to a feedback signal that is generated in response to the output clock signal. A code generator generates a code in response to the input reference signal. A loss detector generates an indication of a loss of the input reference signal in response to the feedback signal and at least two codes generated by the code generator.