Type I PLL Coherence Compensation for Phase-Based Distance Estimation
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Solution Overview
Problem
Phase coherence across different frequencies is challenging in phase-based distance estimation applications, particularly in low-IF receivers, where type-II PLLs increase lock times, in-band noise, power consumption, and circuit size, while type-I PLLs struggle to maintain phase coherency without additional circuitry.
Innovation Solution
A method using a type I PLL with an oscillator and feedback path to estimate a phase correction term, allowing it to operate as a coherent type 2 PLL without a phase error integration block, by determining the total phase shift and applying corrections through a sigma-delta modulator, enabling phase coherence across frequency changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a type-II PLL is used to maintain phase coherence across frequency changes, then phase coherence is improved, but lock time increases
Solution Approach 1:
The patent extracts the phase error integration block from the type-II PLL architecture, retaining only the type-I PLL structure. Phase coherence is maintained through mathematical correction of the steady-state phase lag rather than through integration, eliminating the time penalty associated with type-II PLL locking while preserving phase coherence for distance estimation calculations.
Solution Approach 2:
The patent changes the operational parameters by accepting and correcting for a known steady-state phase lag in the type-I PLL. Instead of attempting to eliminate phase lag through integration (type-II), the system adjusts the phase measurement calculations to account for the predictable phase lag, achieving coherence through parameter compensation rather than structural modification.
2Reliability
If a type-II PLL is used to maintain phase coherence across frequency changes, then phase coherence is improved, but in-band noise increases
Solution Approach 1:
The patent removes the phase error integration block that inherently adds in-band noise to the system. By using type-I PLL without integration and correcting phase measurements through calculation rather than through the integration path, the noise-generating mechanism is eliminated while phase coherence is preserved through mathematical adjustment of the distance estimation algorithm.
3Reliability
If a type-II PLL is used to maintain phase coherence across frequency changes, then phase coherence is improved, but power consumption increases
Solution Approach 1:
The patent eliminates the phase error integration block which consumes additional power in type-II PLL implementations. The type-I PLL structure requires less power, and the phase coherence functionality is achieved through computational correction in the distance estimation algorithm rather than through additional hardware integration, reducing overall power consumption while maintaining measurement accuracy.
4Reliability
If a type-II PLL is used to maintain phase coherence across frequency changes, then phase coherence is improved, but device size increases
Solution Approach 1:
The patent removes the phase error integration block from the PLL circuit, reducing the semiconductor die area required. The type-I PLL structure occupies less space than type-II, and the phase coherence functionality is achieved through algorithmic correction rather than additional integration circuitry, enabling smaller device footprints while maintaining the ability to perform accurate phase-based distance estimation.
5Device complexity
If a type-I PLL is used without additional circuitry, then device complexity is reduced, but phase coherence deteriorates
Solution Approach 1:
The patent introduces a mathematical correction term as an intermediary between the type-I PLL output and the final distance estimation. This correction accounts for the steady-state phase lag without requiring hardware modification to the PLL itself, maintaining circuit simplicity while restoring phase coherence through computational adjustment in the signal processing path.
Solution Approach 2:
The patent compensates for the type-I PLL's inherent phase lag by adjusting the phase measurement parameters in the distance estimation calculation. Rather than modifying the PLL hardware to eliminate phase lag, the system accepts the lag as a known parameter and corrects for it mathematically, maintaining simple circuitry while achieving the required phase coherence for accurate measurements.
Data Source
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AI summary
Disclosed herein are methods of using a type I phase locked loop, PLL, comprising an oscillator and a feedback path to a phase detector. The methods comprise: locking a first frequency and first relative phase of a first output signal to a frequency and a phase of a first input signal; locking a second frequency and second relative phase of a second output signal to a frequency and a phase of a second input signal, estimating a steady state phase lag of the PLL resulting from the difference between the first frequency and the second frequency, using the estimated steady state phase lag, to determine a total phase shift (ΔΦLO,steady) between the second input signal and the second output signal, and a one of: compensating the PLL for the phase shift, and using the determined total phase shift in a distance estimation.