PLL Phase Comparator Merging for Lower Phase Noise
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Solution Overview
Problem
Existing PLL circuits face challenges in reducing phase noise with simple circuitry due to high circuit area and power consumption, particularly in the phase noise region where the division ratio N is significant.
Innovation Solution
A PLL circuit configuration that includes a divider generating a divided signal with a cycle of T/M, a phase comparator performing exclusive logical OR calculations on M+1 signals including the divided signal and M reference signals with sequentially shifted phases, and a loop filter generating a voltage signal for a voltage-controlled oscillator, which reduces the division ratio N and subsequently the phase noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If multiple M phase comparators are arrayed to reduce the division ratio N to 1/M, then phase noise in region 11 is reduced by 1/M^2, but the circuit area and power consumption of the delay circuit and SUM circuit become great
Solution Approach 1:
The patent merges M phase comparators into a single phase comparator that directly calculates the exclusive logical OR of M+1 signals (M reference signals and one divided signal). This consolidation eliminates the need for separate delay circuits and SUM circuits required in conventional multi-phase comparator architectures, thereby reducing circuit area and power consumption while maintaining the phase noise reduction benefit of 1/M^2
Solution Approach 2:
The single phase comparator in the patent performs multiple functions simultaneously: it generates M reference signals with different phases, compares each reference signal with the divided signal, and sums the comparison results all in one integrated circuit. This multi-functional design replaces the conventional separate components (delay circuits for phase shifting and SUM circuits for result aggregation), achieving both phase noise reduction and circuit simplification
Data Source
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AI summary
A PLL circuit includes a divider configured to generate a divided signal having a cycle of T/M (where M is an integer greater than or equal to two) by dividing an oscillation signal; a phase comparator configured to generate a phase comparison result by calculating an exclusive logical OR of M reference signals and the divided signal, the M reference signals having the cycle of T and respective time intervals shifted sequentially by T/2M; a loop filter configured to generate a voltage signal using the phase comparison result as input; and a voltage-controlled oscillator configured to generate the oscillation signal by oscillating at a frequency depending on the voltage signal.