PLL Counter Hold-and-Output Circuit for Accurate High-Speed Counting
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Solution Overview
Problem
Asynchronous counters face transmission delays and timing variations when counting high-frequency clock signals, leading to inaccurate count values, which affects the precision of phase locked loops (PLLs) in determining oscillation frequencies.
Innovation Solution
A counter with a selection unit that selectively outputs a clock signal or a hold signal, allowing the counting unit to hold and output a count value for a desired time, mitigating transmission delays and ensuring accurate counting, and a phase locked loop (PLL) incorporating a voltage-controlled oscillator and frequency state controller to compare oscillation frequencies with a reference frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If asynchronous counters sequentially transmit clock signals through multiple flip-flops, then the counter can count high-frequency clock signals, but transmission delays cause timing variations and inaccurate count values
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing transmission delay compensation values in a delay compensation register before the counting operation. The compensation value is loaded in advance based on the number of flip-flops in the counter, allowing the system to compensate for transmission delays without affecting the real-time counting accuracy of high-frequency clock signals.
Solution Approach 2:
The patent introduces a delay compensation register as an intermediary component between the flip-flops and the output. This register stores and applies compensation values that counteract the transmission delays, acting as a mediator that corrects the timing variations caused by sequential signal transmission through multiple flip-flops.
2Productivity
If flip-flops output count values before completing clock signal transmission, then the counter can respond quickly, but the count values will be inaccurate due to ongoing transmission delays
Solution Approach 1:
The system performs preliminary action by pre-loading the delay compensation value into the delay compensation register before the counting operation begins. This allows the compensation to be applied immediately when count values are output, enabling quick response while maintaining accuracy through pre-prepared correction data.
Solution Approach 2:
The patent implements feedback by using the known transmission delay characteristics of the flip-flop chain to calculate and apply compensation values. The system feeds back the compensation information to correct the count values, ensuring that even when outputting before transmission completes, the final count value is accurate.
3Device complexity
If related art asynchronous counters are used in PLLs, then the PLL can operate with simple counter circuitry, but the PLL cannot precisely determine oscillation frequency due to counting errors
Solution Approach 1:
The PLL system applies preliminary action by pre-calculating the delay compensation value based on the known number of flip-flops in the counter and loading it into the delay compensation register before frequency measurement begins. This allows the simple counter circuitry to produce accurate frequency measurements without adding complex correction logic during operation.
Solution Approach 2:
The delay compensation register serves as an intermediary that bridges the simple counter circuitry and the frequency determination function. It stores and applies compensation values that correct the counting errors, allowing the PLL to achieve precise frequency measurement while maintaining the simplicity of the original counter design.
Data Source
AI summary
Example embodiments may provide a counter capable of outputting a count value after holding the count value for an amount of time and a phase locked loop (PLL) including the counter. The counter may include a selection unit that may selectively output a clock signal and a hold signal in response to a selection signal and a counting unit that may perform a counting operation in response to the clock signal and output a count value obtained by the counting operation after holding the count value for an amount of time in response to the hold signal. The counter may stably output an accurate count value regardless of transmission delays.