PLL Counter Sampling for Accurate Lock Status Detection
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Solution Overview
Problem
Existing phase locked loop (PLL) systems face challenges in monitoring their performance and determining whether they are locked, especially in high-frequency applications, where current technologies struggle to accurately assess the status of the control loop and may experience frequency spikes due to periodic changes in divide ratios.
Innovation Solution
A monitoring circuit that captures counter values at predetermined times, calculates variations using a variability calculator, and outputs a status signal to indicate whether the PLL is locked or unlocked, utilizing a synchronization circuit to align sampling with other signals, and can be applied to both integer and fractional dividers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a phase locked loop operates at high frequency with periodic changes in divide ratios, then frequency multiplication capability is improved, but false lock indications and frequency spikes occur due to inaccurate status monitoring
Solution Approach 1:
The monitoring circuit captures the counter value at a predetermined time point (e.g., at the rising edge of the reference clock) before the divide ratio changes occur. This preliminary capture ensures that the monitored value reflects the actual locked status without being affected by subsequent frequency spikes or transient changes in the divide ratio, thereby preventing false lock indications while maintaining high frequency multiplication capability
Solution Approach 2:
The patent introduces a monitoring circuit as an intermediary component that observes the counter value within the frequency divider. This intermediary provides an indirect but accurate indication of the PLL lock status by monitoring the counter's behavior at critical time points, without directly interfering with the high-frequency operation and divide ratio changes needed for frequency multiplication
2Measurement precision
If the monitoring circuit captures counter values continuously, then monitoring accuracy is improved, but system complexity and resource consumption increase
Solution Approach 1:
The monitoring circuit is designed to capture the counter value only at specific periodic intervals (e.g., at the rising edge of the reference clock or at predetermined time points within the counter cycle). This periodic sampling approach maintains monitoring accuracy by capturing critical status information while significantly reducing the complexity compared to continuous monitoring, as it requires simple timing control rather than continuous measurement infrastructure
Data Source
AI summary
A monitoring circuit for monitoring the performance of a phase locked loop having a divider therein, the divider comprising at least a first counter, the monitoring circuit comprising at least one memory element for capturing a value of the first counter after a predetermined time from a system event in the operation of the phase locked loop, a variability calculator for comparing a value of the counter with a preceding value of the counter to calculate a variation, and a circuit responsive to the estimate of variation for outputting a status signal.