PLL Circuit with DAC Feedforward for Precise Chirp Tracking
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Solution Overview
Problem
Conventional PLL circuits face difficulties in generating high-precision chirp signals, especially when dealing with rapid frequency changes, due to limitations in determining optimal DAC output waveforms and loop filter band variations.
Innovation Solution
A PLL circuit configuration that includes a voltage-controlled oscillator, variable frequency divider, phase frequency comparator, charge pump, loop filter, ΔΣ modulator, first and second frequency accumulators, and a digital-analog converter, where the comparison operating circuit calculates parameters to ensure the comparison result between the accumulators falls within a set value, allowing the DAC to accurately follow frequency changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional PLL circuit uses a loop filter to control the VCO frequency, then the circuit structure is simple, but the frequency followability deteriorates at points where the frequency changes rapidly
Solution Approach 1:
The invention segments the frequency control function into two paths: a main control path through the loop filter for general frequency stability, and a fast control path through the DAC for rapid frequency changes. This segmentation allows each path to optimize for its specific function, improving overall frequency followability without excessive complexity
Solution Approach 2:
The DAC acts as an intermediary component between the frequency accumulator and the VCO, providing a direct frequency adjustment mechanism that bypasses the loop filter's bandwidth limitations. This intermediary enables rapid frequency changes while the loop filter maintains overall stability
2Measurement precision
If the DAC output waveform is manually adjusted to achieve high-precision chirp signal, then the precision can be improved for specific cases, but the adaptability to circuit variations deteriorates
Solution Approach 1:
The frequency accumulator continuously monitors the actual frequency output and adjusts the DAC control signal accordingly to maintain the desired chirp waveform. This feedback mechanism automatically compensates for circuit variations, maintaining both precision and adaptability
Solution Approach 2:
The system uses its own output frequency information (through the frequency accumulator) to automatically adjust its control parameters, eliminating the need for external manual calibration. This self-adjusting capability ensures adaptability to circuit variations while maintaining precision
3Speed
If the loop filter bandwidth is increased to improve frequency followability, then the response to rapid frequency changes is improved, but the phase noise performance deteriorates
Solution Approach 1:
The frequency control function is segmented into two independent control paths: the loop filter path that maintains narrow bandwidth for low phase noise, and the DAC path that provides wide bandwidth for rapid frequency response. This segmentation resolves the trade-off by allowing both performance requirements to coexist
Solution Approach 2:
The system dynamically switches between control paths based on the required response speed. For rapid frequency changes, the DAC path is activated to provide immediate response. For steady-state operation, the loop filter path maintains low phase noise. This dynamic control allows optimal performance in both regimes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables the PLL circuit to effectively cope with steep frequency changes, ensuring the output signal closely matches the ideal waveform by adjusting the DAC output based on the calculated parameters, thereby improving frequency followability.
Implementation Method 1
a voltage-controlled oscillator to transmit a frequency signal corresponding to the voltage of a supplied signal
Implementation Method 2
a loop filter to supply a signal obtained by smoothing the output signal of the charge pump
Data Source
AI summary
A first frequency accumulator (7a) operates using an output signal of a variable frequency divider (3) as a clock. A second frequency accumulator (7b) operates using a reference signal from a reference signal source (1) as a clock. A comparison operating circuit (11) compares the output values of the first frequency accumulator (7a) and the second frequency accumulator (7b), and calculates a parameter so that a result of the comparison falls within a set value. A digital-analog converter (9) outputs a signal to be added to an output of a loop filter (6) depending on the parameter output from the comparison operating circuit (11).