PLL DAC Circuit for Sub-Threshold Leakage Suppression
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Solution Overview
Problem
Phase-locked loops (PLLs) face challenges in generating oscillator signals with satisfactory fidelity at high frequencies due to sub-threshold leakage currents from internal transistors, which alter the frequency of the oscillator signal and lead to poor locking, especially in high-frequency applications (>50 MHz).
Innovation Solution
A digital-to-analog converter (DAC) circuit design utilizing three transistors and a unity gain buffer with a switch configuration that reduces the drain-to-source voltage of the transistors, minimizing sub-threshold leakage currents by ensuring the drain and source voltages are equal, thereby reducing the gate-to-source voltage and minimizing leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If the transistor length (L) is increased to reduce sub-threshold leakage current, then the leakage current is reduced, but the voltage headroom increases and the transistor area increases by 100 times or more
Solution Approach 1:
The patent changes the voltage parameter (drain-to-source voltage) to minimize sub-threshold leakage current. By ensuring the drain and source voltages are equal (Vds = 0), the transistor operates in a state where leakage current is minimized, achieving the desired effect without increasing transistor area.
Solution Approach 2:
The patent applies equipotentiality by making the drain and source voltages equal, creating an equipotential condition between these terminals. This eliminates the voltage differential that causes sub-threshold leakage current, solving the problem without requiring larger transistor dimensions.
2Stress or pressure
If the transistor width (W) is increased to reduce voltage headroom, then the voltage headroom is reduced, but the transistor area increases by 100 times or more
Solution Approach 1:
Instead of changing the geometric parameters (width or length), the patent changes the voltage parameter (drain-to-source voltage) to minimize leakage current. By setting Vds = 0, the patent achieves leakage reduction without modifying transistor dimensions or increasing area.
3Object-generated harmful factors
If the drain-to-source voltage is reduced to minimize sub-threshold leakage current, then the leakage current is reduced, but the current magnitude becomes smaller
Solution Approach 1:
The patent creates an equipotential condition between drain and source (Vds = 0) to eliminate sub-threshold leakage current. This approach minimizes leakage without affecting the gate-controlled current magnitude, as the leakage current is specifically caused by the voltage differential between drain and source.
Data Source
AI summary
A digital to analog converter (DAC) that reduces sub-threshold leakage current in PLLs includes three series connected transistors, a unity gain buffer, and a switch. The system is connected between the voltage-to-current converter and a current-controlled oscillator. The DAC receives and accurately mirrors a current signal generated by a voltage-to-current converter.