PLL Lock Control Using DAC Feedback for Steep Frequency Changes
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Solution Overview
Problem
Conventional PLL circuits face difficulties in coping with steep frequency changes due to variations in VCO and DAC characteristics, making it challenging to stabilize oscillation frequencies effectively.
Innovation Solution
A PLL circuit configuration that includes a lock detector, counter, and parameter controlling circuit to manage the output voltage of a D/A converter and switch, allowing for precise control of the D/A converter's output and switch operation to minimize unlock time and maintain frequency stability during steep frequency changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a D/A converter is connected to a control terminal of a VCO via a switch to supply output during steep frequency changes, then the time required for the PLL to output a correct frequency is shortened, but the characteristics of the VCO and DAC change with process variations and temperature fluctuations, making it difficult to obtain appropriate parameters
Solution Approach 1:
The system automatically determines optimal parameters by having the PLL circuit itself measure its own unlock time and use this information to control the switch duration. The parameter controlling circuit acquires the count value from the counter and uses it to control the switch switching time, creating a self-adjusting system that adapts to process and temperature variations without external calibration.
Solution Approach 2:
The parameter controlling circuit uses feedback from the counter (which measures unlock time) to adjust the switch control signal duration. The count value obtained from the counter during unlock periods is fed back to control the switch switching time in subsequent operations, creating a closed-loop system that optimizes performance based on actual circuit behavior under varying conditions.
2Device complexity
If fixed parameters are used for D/A converter output, then the circuit design is simplified, but the PLL circuit cannot easily cope with output signals with steep frequency changes due to characteristic variations
Solution Approach 1:
The system transitions from fixed parameters to dynamic, adaptive parameters. The switch control signal duration is no longer fixed but is dynamically adjusted based on the count value measured during each unlock event. This allows the system to adapt to varying operating conditions while maintaining relatively simple circuit architecture.
Solution Approach 2:
The system changes the parameter being controlled from a fixed design value to a variable determined by actual circuit performance. The parameter controlling circuit adjusts the switch switching time based on the count value, which reflects actual unlock time under current process and temperature conditions, thereby optimizing performance across different operating points.
Data Source
AI summary
A lock detector (8) detects an unlocked state from an output of a phase frequency comparator (1). A counter (9) counts a reference signal, in a case where an unlocked state is detected by the lock detector (8). A parameter controlling circuit (10) acquires the count value of the counter (9), and controls switching on and off of a switch (12) for a D/A converter (11) that generates a signal to be added to an output of a loop filter (3), and the output voltage of the D/A converter (11) so that the count value of the counter (9) falls within a set value.