PLL Reference Circuit Using DDS Folding Frequencies for Low-Noise Tuning
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Solution Overview
Problem
Conventional PLL circuits face limitations in increasing oscillatory frequency without degrading noise characteristics and suffer from increased power consumption when trying to generate multiple channel outputs, leading to reliability issues.
Innovation Solution
The PLL circuit employs a voltage-controlled oscillator, phase comparison, a DDS circuit that generates folding frequencies, and a variable filter to produce a desired reference signal over a wide range, using external amplification and filter settings to maintain noise quality and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the division ratio in the PLL IC is increased to increase the oscillatory frequency, then the oscillatory frequency is improved, but the noise characteristics are degraded
Solution Approach 1:
The patent applies dynamics by making the DDS output frequency variable and using folding frequency generation to adaptively achieve different oscillatory frequencies without relying solely on increasing the division ratio. The system dynamically adjusts the DDS output frequency and selects appropriate folding frequencies to maintain noise characteristics while achieving high oscillatory frequencies.
Solution Approach 2:
The patent changes the parameter of DDS output frequency to generate folding frequencies that can be used as reference signals. By varying the DDS output frequency and selecting different folding frequencies (e.g., 2Fref±Fdds, 3Fref±Fdds), the system achieves different oscillatory frequencies without necessarily increasing the division ratio, thus maintaining noise characteristics.
2Adaptability or versatility
If the DDS circuit output frequency is increased to generate multiple channel outputs, then the frequency selection range is improved, but the power consumption is increased
Solution Approach 1:
The patent converts the harmful effect of high DDS output frequency (which increases power consumption) into a benefit by utilizing folding frequency generation. Instead of directly using high frequencies that consume more power, the system generates folding frequencies from lower DDS output frequencies, achieving wide frequency selection range while suppressing power consumption.
Solution Approach 2:
The patent introduces folding frequency generation as an intermediary mechanism between the DDS circuit and the VCO. The folding frequency (e.g., 2Fref±Fdds, 3Fref±Fdds) acts as a mediator that allows the system to achieve high oscillatory frequencies without directly operating the DDS circuit at high frequencies, thus reducing power consumption while maintaining frequency selection range.
3Speed
If the DDS circuit output frequency is increased to increase the oscillatory frequency, then the oscillatory frequency is improved, but the reliability is degraded
Solution Approach 1:
The patent uses folding frequency generation as an intermediary to decouple the relationship between DDS output frequency and oscillatory frequency. The folding frequency serves as a mediator that allows the VCO to operate at high frequencies without requiring the DDS circuit to operate at equally high frequencies, thereby improving reliability while achieving high oscillatory frequencies.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for improved reliability and reduced power consumption while maintaining noise characteristics, enabling a fine and wide range of frequency selection without degrading noise performance.
Implementation Method 1
a voltage controlled oscillator that outputs a desired oscillatory frequency in accordance with a control voltage
Implementation Method 2
phase comparison means that frequency-divides an output of the voltage controlled oscillator, compares phase between the output and a reference signal and outputs a signal based on a phase difference as a control voltage
Implementation Method 3
a direct digital synthesizer (DDS) circuit that outputs, to the PLL IC, an output frequency generated based on the reference frequency from the reference oscillator
Implementation Method 4
The analog filter 3 smoothes the divided frequency from the PLL IC 2 and outputs the same as a control voltage to the VCO 1
Data Source
AI summary
Provided is a PLL circuit improving reliability while suppressing power consumption without degrading noise characteristics. The PLL circuit includes a PLL IC that divides an output frequency Fout from a VCO, compares phase with a reference signal, and feeds back a phase difference as a control voltage to the VCO. A control circuit is capable of finely setting both of a reference frequency Fref and an output frequency Fdds in a DDS circuit, and the DDS circuit generates folding signals of Fdds for Fref and an integral multiple frequency thereof based on the combination of the frequencies. A first AMP amplifies a signal, a variable filter selects a desired Fdds (desired) and a second AMP amplifies the signal and supplies the same to the PLL IC as a reference signal. The control circuit further supplies a division ratio N to the PLL IC.