Multi-Mode PLL Circuit for Low-Noise Dead Time Control
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Solution Overview
Problem
Conventional phase-locked loop (PLL) circuits are limited by noise multiplication and jitter-power factor, and lack versatility to operate in different modes for various applications, necessitating an improved circuit design that can adjust duty cycles and control dead time accurately.
Innovation Solution
A phase-locked loop circuit with a phase adjustment circuit capable of operating in duty cycle adjustment and delayed phase-locked loop modes, incorporating a delay phase-locked loop and sub-sampling phase-locked loop with phase correction, sub-sampling phase detection, and phase frequency detection circuits to control dead time, reducing noise and jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a conventional PLL with N-divider on feedback path is used, then frequency multiplication is achieved, but phase noise is multiplied by N^2 and jitter-power factor is limited
Solution Approach 1:
The PLL is segmented into two independent loops: a delay-locked loop (DLL) for duty cycle correction and a sub-sampling PLL for frequency multiplication. The DLL processes the reference clock separately from the VCO feedback path, eliminating noise multiplication while maintaining frequency multiplication capability in the sub-sampling PLL.
Solution Approach 2:
A duty cycle correction circuit is introduced as an intermediary between the reference clock and the sub-sampling phase detector. This intermediary circuit corrects duty cycle errors without being part of the high-frequency feedback path, thereby preventing noise multiplication while ensuring accurate phase detection.
2Device complexity
If a single-function PLL circuit is used, then circuit design is simple, but it cannot operate in different modes for different applications
Solution Approach 1:
The phase adjustment circuit is designed with multi-functionality to operate in both duty cycle adjustment mode and delay phase-locked loop mode. The same circuit hardware can be configured for different applications through control signals, eliminating the need for separate circuits for each function and maintaining design simplicity while achieving versatility.
Solution Approach 2:
The circuit employs dynamic switching between different operational modes through control signals. The phase adjustment circuit can dynamically transition between duty cycle correction mode and phase delay mode based on application requirements, allowing a single circuit to adapt to different scenarios without physical reconfiguration.
3Reliability
If duty cycle adjustment is performed in conventional PLL, then phase alignment is improved, but dead time control precision is insufficient
Solution Approach 1:
The circuit replaces conventional mechanical or analog dead time control mechanisms with a digital-based phase frequency detection circuit. This digital approach uses precise counting and logic operations to determine dead time, achieving superior precision compared to traditional analog methods while maintaining accurate phase alignment.
Data Source
AI summary
A motor driving device includes a first hysteresis comparator, a second hysteresis comparator, a logic circuit, a control unit, and an inverter circuit. The logic circuit receives a start signal or a start completion signal to output the first output signal as a commutation signal according to the start signal, or to output the second output signal as the commutation signal according to the start completion signal, clamps the second output signal by the first output signal, stops outputting the commutation signal after the potential state of the commutation signal is changed, and unclamps the second output signal with the first output signal and outputs the commutation signal in response to a difference voltage between the first input signal and the second input signal being greater than a positive value of the first hysteresis voltage or less than a negative value of the first hysteresis voltage.