PLL Frequency Correction Loop With Deadzone and Hysteresis Locking

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Solution Overview

Problem

Phase lock loops (PLLs) face challenges with high power consumption, noise generation, and non-linearities due to feedback dividers and charge pumps, leading to increased jitter and phase noise, especially at higher frequencies.

Innovation Solution

Implementing a frequency correction loop with a deadzone and hysteresis in the phase lock loop to control the activation and deactivation of the charge pump based on phase differences, using a phase detector with programmable delay parameters to stabilize the loop and reduce false locking.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If feedback divider ratio is increased to achieve frequency locking at higher VCO frequencies, then frequency locking capability is improved, but power consumption and noise increase

Engineering Contradiction:

ImproveVCO frequencyVSAvoidfeedback divider power consumption

Core Design Contradiction:

SpeedVSUse of energy by stationary object

Solution Approach 1:

The patent divides the frequency locking function into two separate loops: a primary PLL for basic frequency locking and a frequency correction loop (FCL) for fine-tuning. The FCL uses a separate charge pump (second charge pump) that operates independently from the main charge pump, allowing frequency adjustments without continuously driving the main feedback divider at high ratios, thereby reducing its average power consumption and noise generation.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a frequency correction loop as an intermediary mechanism between the reference frequency and the VCO. This FCL acts as a mediator that makes small frequency adjustments to the VCO output, reducing the need for the main feedback divider to operate at extreme ratios, thus lowering its power consumption and noise while maintaining accurate frequency locking.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If charge pump gain is increased to improve PLL gain and noise performance, then PLL gain is improved, but device size and power consumption increase

Engineering Contradiction:

ImprovePLL gain and noise performanceVSAvoidcharge pump power consumption

Core Design Contradiction:

ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The patent segments the charge pump functionality into two distinct charge pumps: a main charge pump for primary frequency locking and a second charge pump specifically for frequency correction. This segmentation allows the second charge pump to operate with optimized, lower current levels for fine-tuning operations, reducing overall power consumption while maintaining the necessary PLL gain through coordinated operation of both charge pumps.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The frequency correction loop applies only the necessary amount of frequency adjustment (partial action) rather than continuously applying maximum correction. The FCL activates only when frequency deviations are detected and applies corrective current proportional to the deviation magnitude, avoiding excessive charge pump operation and reducing average power consumption while maintaining adequate PLL gain when needed.

Inventive Principle:

Principle #16Partial or excessive action

3Reliability

If feedback divider ratio is increased for tighter phase noise requirements, then phase noise performance is improved, but feedback divider size and power consumption increase

Engineering Contradiction:

Improvephase noise performanceVSAvoidfeedback divider size

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent segments the frequency control function so that the main feedback divider operates at moderate ratios for basic locking, while a frequency correction loop with its own divider operates at higher effective ratios for fine frequency adjustments. This segmentation allows achieving tight phase noise requirements through the coordinated action of both dividers rather than requiring a single large-ratio divider, thereby reducing the size of individual divider circuits.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent adds another dimension to the frequency control system by introducing a nested frequency correction loop within the main PLL structure. This creates a hierarchical frequency control architecture where the FCL operates as an inner loop that makes fine adjustments, effectively increasing the overall frequency resolution and phase noise performance without requiring the main feedback divider to operate at extremely high ratios, thus reducing its size.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20260051893A1Frequency correction loop with deadzone and hysteresis

Publication Date: 2026.02.19 RENESAS ELECTRONICS AMERICA INC

AI summary

Semiconductor devices for synchronizing networks are described. A semiconductor device can include a phase lock loop of a timing circuit. The phase lock loop includes a voltage-controlled oscillator, a sub-sampling phase lock loop circuit and a frequency correction loop circuit. The frequency correction loop circuit is configured to activate a charge pump to inject a charge into the voltage-controlled oscillator based on a phase difference between a reference signal and a feedback signal being greater in magnitude than a deadzone delay parameter plus a hysteresis delay parameter and de-activate the charge pump based on the magnitude of the phase difference between the reference signal and the feedback signal falling below the deadzone delay parameter.