Charge-Pump PLL Decimation for Stability Without Large Capacitors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional charge-pump phase-locked loop (PLL) circuits face challenges in stability, which is improved by increasing capacitance, but this results in increased costs and larger circuit area.
Innovation Solution
The implementation of a decimator in the charge-pump PLL circuit allows for capacitance multiplication by generating a decimated version of phase error information, effectively increasing the equivalent capacitance without the need for larger physical capacitors, thereby achieving stability with a reduced circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the capacitance of the integral charge pump path is increased to improve stability, then the stability of the charge pump PLL is improved, but the circuit area and cost increase
Solution Approach 1:
The patent changes the operational parameters of the charge pump by introducing a decimator that generates decimated versions of phase error information at different decimation factors. This allows the system to achieve stability through parameter variation (decimation factor N) rather than increasing capacitance, thereby resolving the contradiction between stability and circuit area
Solution Approach 2:
The patent introduces dynamic elements including a decimator that can operate at different decimation factors and a voltage adder that dynamically combines voltages from different charge pump paths. This dynamic operation allows the system to achieve stability without requiring large fixed capacitance values, thus reducing circuit area while maintaining stability
Data Source
AI summary
A phase-locked loop circuit. The phase-locked loop circuit comprises a phase detector, a proportional charge pump, a decimator, an integral charge pimp, and a voltage-controlled oscillator. The phase detector obtains an phase error information according to a phase difference between a reference signal and a clock signal input to the phase detector. The proportional charge pump coupled to the phase detector generates a first voltage according to the phase error information. The decimator generates a decimated version of the phase error information by a decimation factor of N. The integral charge pump generates a second voltage according to the decimated version of the phase error information. The voltage-controlled oscillator generating the clock signal according to a combination of the first and second voltages.