PLL Delay Cell Current Control for Wide-Range Low-Jitter Clocks
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Solution Overview
Problem
Semiconductor memory devices face challenges in generating an internal clock with stable frequency and improved jitter characteristics due to variations in process, voltage, and temperature (PVT) conditions, leading to unintended output frequencies and deteriorated jitter characteristics.
Innovation Solution
A phase locked loop (PLL) with a delay cell that includes a first current controller, signal input unit, and second current controller, which adjusts currents based on control voltage and frequency range selection signals to maintain stable delay time and frequency across varying PVT conditions, thereby improving jitter characteristics and maintaining frequency within a target range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional voltage controlled oscillator is used to generate the internal clock, then the frequency can be adjusted according to control voltage, but the jitter characteristics deteriorate and unintended output frequencies occur due to PVT variations
Solution Approach 1:
The voltage controlled oscillator is segmented into multiple delay cells connected in series, where each delay cell contributes a specific delay amount to the overall oscillation period. This segmentation allows independent optimization of each delay cell's characteristics while maintaining the overall frequency adjustment capability, thereby improving jitter characteristics.
Solution Approach 2:
Each delay cell is designed with specific local characteristics (different delay amounts) to compensate for PVT variations. The delay cells are configured with different transistor sizes and configurations to create localized delay characteristics that collectively achieve stable frequency output across varying PVT conditions.
2Speed
If the delay value of delay cells is reduced to increase output frequency, then higher frequency is achieved, but the jitter characteristics deteriorate
Solution Approach 1:
The system dynamically selects and configures delay cell characteristics based on operating conditions. The delay cells can be selectively enabled or disabled, and their delay amounts can be adjusted dynamically to maintain optimal jitter characteristics across different frequency ranges, allowing high frequency operation without jitter deterioration.
3Adaptability or versatility
If the frequency range of the internal clock is expanded, then wider frequency coverage is achieved, but the jitter characteristics deteriorate at high frequencies
Solution Approach 1:
The delay cell parameters (transistor sizes, channel lengths, bias currents) are specifically designed and optimized to maintain consistent delay characteristics across a wide frequency range. By carefully controlling these parameters, the system achieves wide frequency coverage while maintaining stable jitter characteristics even at high frequencies.
Data Source
AI summary
A phase locked loop that generates an internal clock by controlling a delay time of a delay cell according to conditions of PVT, thereby improving a jitter characteristic of the internal clock. The delay cell includes a first current controller for controlling first and second currents in response to a control voltage, and a second current controller for controlling the first and second currents in response to frequency range selection signals. The phase locked loop includes a phase comparator for comparing a reference clock with a feedback clock, a control voltage generator for generating a control voltage corresponding to an output of the phase comparator, and a voltage controlled oscillator for generating an internal clock having a frequency in response to the control voltage and one or more frequency range control signals, wherein the feedback clock is generated using the internal clock.