Variable-Length PLL Delay Chain for Precise Low-Power Locking
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Solution Overview
Problem
Existing phase-locked loops in high bit-rate and low consumption transmission systems, such as IR-UWB technology, face challenges in optimizing energy efficiency, particularly in phase-locked loops that contribute significantly to the energy budget.
Innovation Solution
A phase-locked loop circuit with a delay chain formed by cascade-connected flip-flops, multiplexers, and control circuits that adjust the length of a circular shift register electronically, allowing for variable delay and optimizing energy consumption by controlling voltage and shift register length to achieve precise locking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the phase-locked loop uses a fixed-length delay chain, then the circuit structure is simple, but the locking precision and adaptability are limited
Solution Approach 1:
The patent implements a variable-length delay chain where the number of delay elements can be dynamically adjusted through control signals. This allows the phase-locked loop to adapt the delay period to different frequency requirements, improving locking precision while maintaining a relatively simple circuit structure through systematic design of the delay elements.
Solution Approach 2:
The patent changes the parameter of delay chain length to optimize performance. By controlling the number of active delay elements (e.g., switching between 15, 16, or 17 elements), the system can adjust the phase delay to achieve precise frequency locking without requiring completely different circuit designs for each application scenario.
2Reliability
If the phase-locked loop operates continuously to maintain locking, then the locking stability is high, but the energy consumption increases
Solution Approach 1:
The patent employs periodic monitoring and adjustment mechanisms where the phase-locked loop checks locking status at intervals and only makes adjustments when necessary. This allows the system to maintain locking stability while consuming less energy compared to continuous active adjustment, as the delay chain length is modified only when phase error detection indicates a need for correction.
Solution Approach 2:
The phase-locked loop incorporates automatic phase error detection and correction mechanisms that operate autonomously. The system self-regulates by detecting phase differences and automatically adjusting the delay chain configuration, reducing the need for external control intervention and minimizing energy consumption while maintaining stable operation.
3Measurement precision
If the phase-locked loop uses a longer delay chain to improve precision, then the locking accuracy increases, but the response time increases
Solution Approach 1:
The patent implements dynamic switching capability that allows the delay chain length to be adjusted based on operational requirements. When fast response is needed, the system can use a shorter effective delay chain; when high precision is required, it can extend the delay chain. This dynamic adaptability resolves the trade-off between response time and locking accuracy.
Solution Approach 2:
The delay chain is divided into multiple segmentable units that can be selectively activated. Instead of using a single long fixed delay chain, the system employs multiple smaller delay elements that can be configured in different combinations, allowing the system to achieve the necessary precision with minimal total delay, thus reducing response time while maintaining accuracy.
Data Source
AI summary
A Phase-locked loop circuit including: a local oscillator, configured to generate a timing signal; a variable-length shift register, controlled by the timing signal; and a feedback control circuit, which receives a pulsed input signal and receives a local signal from the shift register. The feedback control circuit detects whether each pulse of the input signal respects a condition of temporal proximity with a corresponding pulse of the local signal and detects, for each pulse of the input signal that respects the proximity condition, whether the edge falls early, late, or within a predefined portion of the corresponding pulse of the local signal. The feedback control circuit controls the length of the shift register and the frequency of the timing signal, as a function of the detections made.