PLL Feedback Delay Circuit for Shorter Lock Time and Stability
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Solution Overview
Problem
Phase locked loops (PLLs) face challenges in achieving a short lock time while maintaining stability, as increasing loop gain can lead to increased lock time and instability, particularly in charge pump PLLs.
Innovation Solution
Incorporating a delay circuit between the N divider circuit and the phase detector in the feedback path of the PLL, which allows for increased loop gain to reduce lock time without causing instability, by adjusting the delay based on loop gain and reducing it after locking to minimize jitter and ensure stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If loop gain is increased to reduce lock time, then lock time is reduced, but stability deteriorates and lock time may increase
Solution Approach 1:
A delay circuit is introduced as an intermediary element in the feedback path between the N divider circuit and phase detector. This delay circuit acts as a mediator that modifies the feedback signal timing, enabling the system to achieve reduced lock time through increased loop gain while maintaining stability by compensating for phase shifts and preventing oscillations that would otherwise occur with high loop gain configurations.
2Loss of time
If loop gain is increased to reduce lock time, then lock time is reduced, but charge pump current increases causing overcompensation
Solution Approach 1:
The delay circuit serves as an intermediary that regulates the feedback signal timing, allowing the charge pump to operate at higher currents for faster locking without causing overcompensation. By introducing controlled delay, the system can tolerate higher charge pump currents while maintaining proper phase relationships, thus achieving reduced lock time without the harmful overcompensation effect.
Solution Approach 2:
The delay circuit introduces dynamic timing adjustment to the feedback path, enabling the system to adaptively manage charge pump current effects. This dynamic approach allows the PLL to benefit from high loop gain during the locking phase while preventing overcompensation through the timing adjustments provided by the delay circuit.
Data Source
AI summary
Increasing loop gain is a common practice for reducing lock time of phase locked loops. Very high loop gains, however, often result in increasing the lock time or causing loop instability. For very high loop gains, delaying the feedback clock signal along the feedback path of a phase locked loop decreases lock time and prevents instability. A delay circuit may be used at any location along the feedback path of the phase locked loop.