PLL Multiplexer Delay Gating for Glitch-Free Clock Switching
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Solution Overview
Problem
Dynamic Voltage Frequency Scaling (DVFS) techniques in processors often introduce glitches when switching between phase-locked loops (PLLs), leading to functional failures due to truncated pulses during frequency changes.
Innovation Solution
A glitch-free PLL multiplexer circuit that switches between phase-locked clocks of multiple PLLs without requiring any phase or frequency relationship, using delay circuits and logical gates to ensure glitch-free operation by alternately enabling input enables and employing propagated enables to gate propagation, allowing seamless switching between PLLs within 1-2 cycles of the second PLL's frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a PLL multiplexer switches between phase-locked loops to enable dynamic frequency scaling, then frequency switching capability is improved, but glitches and truncated pulses are introduced during switching
Solution Approach 1:
The patent applies preliminary action by delaying the propagation of enable signals before switching between PLLs. The delay circuits hold the enable signals in a stable state during the transition period, ensuring that the output clock switches cleanly between PLLs without introducing glitches or truncated pulses. This preliminary timing adjustment prevents harmful switching artifacts.
2Reliability
If delay circuits are introduced to gate propagation of enable signals, then switching reliability is improved, but device complexity increases
Solution Approach 1:
The patent segments the enable signal propagation path into multiple controlled stages using separate delay circuits for each PLL. Each delay circuit independently controls the enable signal for its associated PLL, allowing precise timing control without requiring complex global timing logic. This segmentation simplifies the overall control architecture while achieving reliable glitch-free switching.
Data Source
AI summary
A circuit and corresponding method enable glitch-free frequency. The circuit comprises a first delay circuit and a second delay circuit, configured to produce first and second propagated enables, respectively, from first and second input enables, respectively; and an output clock circuit. The output clock circuit is configured to produce an output clock that switches, glitch-free, between a first phase-locked clock and a second phase-locked. The first and second delay circuits are further configured to enable the output clock to be switched, glitch-free, by employing the second propagated enable to gate propagation of the first input enable and the first propagated enable to gate propagation of the second input enable, respectively. The first and second input enables are configured to be enabled, alternately, causing the output clock to switch between the first and second phase-locked clocks.