PLL Feed-Forward Delay Loop for Phase Noise Jitter Reduction
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Solution Overview
Problem
Phase noise in telecommunications leads to undesirable phase-noise jitter in phase-locked loops, reducing the reliability and data rates of telecommunication circuits, and existing methods are insufficient to effectively address this issue, especially in intermediate frequencies.
Innovation Solution
A feed-forward loop circuit that includes a phase frequency detector, a time to voltage conversion circuit, and a voltage controlled delay line, which compares the edges of a reference clock and a phase locked loop output, converts time differences into voltage signals, and uses these signals to introduce controlled delays, thereby reducing jitter in the output signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a phase-locked loop is used to synchronize the phase of an incoming signal with a reference clock, then phase synchronization is achieved, but phase noise causes undesirable jitter in the output
Solution Approach 1:
The patent implements a feedback mechanism where the phase detector continuously monitors the phase difference between the reference clock and the divided VCO output, generates correction signals, and feeds them back to the delay element to dynamically adjust and eliminate jitter in real-time
Solution Approach 2:
The patent introduces a delay element as an intermediary component between the VCO and the output, controlled by a feedback mechanism, to compensate for and eliminate jitter without directly modifying the VCO operation
2Object-generated harmful factors
If traditional phase-locked loop methods are used to reduce jitter, then some jitter reduction is achieved, but the methods are insufficient especially in intermediate frequencies
Solution Approach 1:
The patent employs dynamic components including a voltage-controlled delay element and a phase detector that continuously adapts to different frequency conditions, enabling effective jitter reduction across a wide frequency range including intermediate frequencies where traditional methods fail
3Speed
If a voltage controlled oscillator generates high frequency output, then the output frequency is increased, but phase noise and jitter are introduced
Solution Approach 1:
The patent extracts and separates the jitter compensation function from the frequency generation function by introducing an independent feedback loop with a delay element, allowing the VCO to operate at high frequencies while the feedback mechanism independently removes phase noise and jitter from the output
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The feed-forward loop significantly improves phase-noise performance of phase-locked loops by reducing time interval error (jitter) without compromising other critical performance parameters, as demonstrated by simulations showing a greater than three-fold improvement in jitter reduction across various temperature and process variations.
Implementation Method 1
The PFD detects a time difference between the edges of the reference clock and the output of the PLL circuit
Implementation Method 2
The time to voltage conversion circuit is configured to change a voltage on a voltage line an amount proportional to the time difference
Implementation Method 3
The voltage controlled delay line delays the output of the PLL circuit an amount of time based on the magnitude of the voltage received from the time to voltage conversion circuit
Data Source
AI summary
A method and apparatus for reducing the amount of jitter in a signal are disclosed. In one embodiment a feed-forward loop compares the edges of a reference clock and an input signal, converts a time difference of the compared edges into a voltage signal, and controls a time delay in a voltage controlled delay line in order to reduce or eliminate jitter.