PLL Frequency Detection with Asynchronous Delay Against Metastability
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Solution Overview
Problem
Semiconductor memory devices face issues with metastability in clock signal adjustment circuitry, leading to erroneous detection of frequency or phase deviations, which can affect the reliability of operations dependent on the clock signal.
Innovation Solution
Incorporating an input delay circuit within the frequency detector of the PLL circuit to introduce an asynchronous timing delay, reducing the likelihood of metastable conditions by offsetting signal transitions and improving the reliability of clock input and generation circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If clock signal adjustment circuitry detects phase or frequency deviation to correct timing, then timing accuracy is improved, but metastable conditions cause erroneous detection leading to actual frequency or phase deviation
Solution Approach 1:
The frequency detector resets the divider circuit before detecting frequency deviation. This preliminary reset action ensures that the divider circuit starts from a known state, preventing metastable conditions from causing erroneous detection. The reset occurs prior to the detection process, eliminating the harmful interaction between metastability and frequency measurement.
Solution Approach 2:
The patent introduces a reset mechanism that cushions against the harmful effects of metastability by preparing the divider circuit in advance. Before frequency detection begins, the reset circuit clears any potential metastable states, creating a protective buffer that prevents erroneous detection and subsequent clock signal deviation.
2Speed
If the divider circuit runs concurrently with frequency detection, then detection speed is improved, but metastable conditions from signal transitions cause erroneous detection
Solution Approach 1:
The divider circuit is reset before frequency detection begins, establishing a clean initial state. This preliminary reset prevents metastable conditions that would otherwise occur during concurrent operation, allowing the system to maintain both speed and accuracy by eliminating the harmful interaction between simultaneous signal transitions and detection.
Data Source
AI summary
A phase-locked loop (PLL) circuit is configured to adjust a value of a bias voltage based on a comparison between a reference clock signal and a feedback clock signal, and an oscillator circuit is configured to provide the feedback clock signal and phase-shifted clock signals based on a value of the bias voltage. A frequency detector of the frequency detector is configured to cause an adjustment to the value of the bias voltage in response to detection of a frequency deviation between the reference clock signal and the feedback clock signal. To avoid a metastable state, the frequency detector is configured to apply an asynchronous delay to one of the reference clock signal or the feedback clock signal prior to detection of the frequency deviation.